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Entry Level Asic Rtl Design Engineer Jobs in Seattle, WA

Amazon

FPGA Engineer, Amazon LEO OISL

Redmond, WA

$145.60K - $187K/yr

... design engineer will work with systems teams to define/develop/implement/test/release FPGA based ... RTL Design-Physical Implementation-Timing Closure-Simulation Validation- Lab Based Silicon ...

Amazon

FPGA Engineer, Amazon LEO OISL

Redmond, WA · On-site

$145.60K - $187K/yr

... design engineer will work with systems teams to define/develop/implement/test/release FPGA based ... RTL Design-Physical Implementation-Timing Closure-Simulation Validation- Lab Based Silicon ...

Amazon

FPGA Engineer, LEO Payload FPGA

Redmond, WA · On-site

$145.60K - $187K/yr

... design engineer will work with systems teams to define/develop/implement/test/release FPGA based ... RTL Design-Physical Implementation-Timing Closure-Simulation Validation- Lab Based Silicon ...

Amazon

Sr. FPGA Engineer, Amazon Leo

Redmond, WA

$145.60K - $187K/yr

... ASIC design teams to support RTL development and verification - Mentor junior engineers and provide technical leadership on FPGA best practices - Work with cross-functional teams including system ...

Amazon

Sr. FPGA Engineer, Amazon Leo

Redmond, WA

$145.60K - $187K/yr

... ASIC design teams to support RTL development and verification - Mentor junior engineers and provide technical leadership on FPGA best practices - Work with cross-functional teams including system ...

PCS STRUCTURAL SOLUTIONS INC

Design Engineer

Tacoma, WA · On-site

PCS Structural Solutions is looking to welcome an entry level Design Engineer to our team! We're looking for mission-driven individuals to join our collaborative and innovative team! At our firm, you ...

legence

Mechanical Design Engineer

Renton, WA

$85.50K - $115.90K/yr

Entry Level Mechanical Engineer Employment Type: Full-Time Schedule: In Office M-F Salary: $80,200 ... This individual will be working with a team to design, analyze, and coordinate the mechanical ...

legence

Mechanical Design Engineer

Renton, WA · On-site

$85.50K - $115.90K/yr

Entry Level Mechanical Engineer Employment Type: Full-Time Schedule: In Office M-F Salary: $80,200 ... This individual will be working with a team to design, analyze, and coordinate the mechanical ...

SpaceX

RFIC Design Engineer (RFIC Engineering)

Redmond, WA · On-site

$145K - $175K/yr

RFIC DESIGN ENGINEER (RFIC ENGINEERING) At SpaceX we're leveraging our experience in building ... Work with system architects, modem/DSP and ASIC engineers to partition functions between hardware ...

Legence

Mechanical Design Engineer

Renton, WA · On-site

$80.20K - $83K/yr

... Entry Level Mechanical Engineer Employment Type: Full-Time Schedule: In Office M-F Salary: $80,200 ... This individual will be working with a team to design, analyze, and coordinate the mechanical ...

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All JobsEntry Level Asic Rtl Design Engineer JobsEntry Level Asic Rtl Design Engineer Jobs in Seattle, WA

Entry Level Asic Rtl Design Engineer information

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$107K

$170.9K

$229.9K

How much do entry level asic rtl design engineer jobs pay per year?

As of May 30, 2026, the average yearly pay for entry level asic rtl design engineer in Seattle, WA is $170,926.00, according to ZipRecruiter salary data. Most workers in this role earn between $149,600.00 and $204,800.00 per year, depending on experience, location, and employer.

What are the key skills and qualifications needed to thrive as an Entry Level ASIC RTL Design Engineer, and why are they important?

To thrive as an Entry Level ASIC RTL Design Engineer, you need a solid background in digital logic design, computer architecture, and proficiency in hardware description languages like Verilog or VHDL, typically supported by a degree in electrical or computer engineering. Familiarity with EDA tools such as Synopsys or Cadence, and understanding of simulation, synthesis, and verification flows are commonly required. Strong problem-solving abilities, attention to detail, and effective teamwork and communication skills help individuals excel in this role. These skills enable accurate and efficient hardware design, seamless integration with larger teams, and successful delivery of complex semiconductor products.

What are some typical challenges faced by Entry Level ASIC RTL Design Engineers in their first year, and how can they overcome them?

Entry Level ASIC RTL Design Engineers often encounter challenges such as understanding complex design specifications, learning company-specific design flows and tools, and debugging RTL code efficiently. Collaborating closely with senior engineers and participating in code reviews can accelerate learning and help address these challenges. Additionally, taking initiative to study relevant documentation and seeking feedback regularly will help new engineers build confidence and technical competence in their role.

What does an Entry Level ASIC RTL Design Engineer do?

An Entry Level ASIC RTL (Register Transfer Level) Design Engineer is responsible for designing and developing the digital logic that forms the core of Application Specific Integrated Circuits (ASICs). They use hardware description languages like Verilog or VHDL to create and simulate circuit designs based on functional specifications. Their tasks often include coding, debugging, verification, and collaborating with senior engineers to ensure the design meets performance, power, and area requirements. This role is essential for bringing complex digital systems from concept to physical implementation in products such as processors, networking chips, and other specialized electronics.

What is the difference between Entry Level Asic Rtl Design Engineer vs Digital Design Engineer?

AspectEntry Level Asic Rtl Design EngineerDigital Design Engineer
Required CredentialsBachelor's in Electrical Engineering or Computer Engineering; knowledge of HDL (Verilog/VHDL)Bachelor's in Electrical Engineering, Computer Engineering, or related; HDL knowledge often required
Work EnvironmentSemiconductor companies, chip design teams, hardware development labsElectronics companies, integrated circuit design teams, hardware development labs
Industry UsagePrimarily in ASIC/FPGA chip designIn digital hardware design across various sectors including consumer electronics and telecom

While both roles involve digital hardware design and HDL skills, the Entry Level Asic Rtl Design Engineer focuses specifically on ASIC chip development, whereas the Digital Design Engineer may work on a broader range of digital systems, including FPGA and other digital hardware projects.

What are the most commonly searched types of Asic Rtl Design Engineer jobs in Seattle, WA? The most popular types of Asic Rtl Design Engineer jobs in Seattle, WA are:
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What cities near Seattle, WA are hiring for Entry Level Asic Rtl Design Engineer jobs? Cities near Seattle, WA with the most Entry Level Asic Rtl Design Engineer job openings:
Entry Level Asic Rtl Design Engineer jobs near you
Infographic showing various Entry Level Asic Rtl Design Engineer job openings in Seattle, WA as of May 2026, with employment types broken down into 100% Full Time. Highlights an 100% In-person job distribution, with an average salary of $170,926 per year, or $82.2 per hour.
FPGA/ASIC Design Engineer (Silicon Engineering)

FPGA/ASIC Design Engineer (Silicon Engineering)

SpaceX

Redmond, WA • On-site

$140K - $175K/yr

Full-time

Medical, Dental, Vision, Life, Retirement, PTO

Posted 9 days ago

SpaceX rating

8.7

Company rating: 8.7 out of 10

Based on 142 frontline employees who took The Breakroom Quiz

12th of 59 rated aerospace companies

Job description

SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars.
FPGA/ASIC DESIGN ENGINEER (SILICON ENGINEERING)
At SpaceX we're leveraging our experience in building rockets and spacecraft to deploy Starlink, the world's most advanced broadband internet system. Starlink is the world's largest satellite constellation and is providing fast, reliable internet to millions of users worldwide. We design, build, test, and operate all parts of the system - thousands of satellites, consumer receivers that allow users to connect within minutes of unboxing, and the software that brings it all together. We've only begun to scratch the surface of Starlink's potential global impact and are looking for best-in-class engineers to help maximize Starlink's utility for communities and businesses around the globe.
We are seeking a motivated, proactive, and intellectually curious engineer who will work alongside world-class cross-disciplinary teams (systems, firmware, architecture, design, validation, product engineering, ASIC implementation). In this role, you will be developing cutting-edge next-generation FPGAs and ASICs for deployment in space and ground infrastructures around the globe. These chips are enabling connectivity in places it has previously not been available, affordable or reliable. Your efforts will help deliver cutting-edge solutions that will expand the performance and capabilities of the Starlink network.
RESPONSIBILITIES:
  • Design ASICs and/or FPGAs for Starlink projects, implementing complex SoC blocks and SoC integration tasks using Verilog/SystemVerilog
  • Optimize designs for power, performance and area
  • Participate in the full ASIC/FPGA design lifecycle for Starlink projects, from high-level conceptual and architectural discussions through microarchitecture, design partitioning, and collaboration with backend/implementation teams, and assist in lab bring-up and validation
  • Contribute to continual improvements to our designs by building physical and digital tools to analyze data collected on orbit and in the lab
  • Engage in high-level architectural design for test systems to support FPGA/ASIC validation, generational interoperability, and integration with DSP/communications subsystems for comprehensive lab and on-orbit verification.
  • Collaborate with software engineers in developing production software for your designs

BASIC QUALIFICATIONS:
  • Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or Physics
  • 1+ years of experience in RTL Design using SystemVerilog, Verilog or VHDL

PREFERRED SKILLS AND EXPERIENCE:
  • ASIC/FPGA system integration experience
  • Proficiency in Python, C/C++, and Bash
  • Experience in designing DSP, digital communication system datapath blocks, and/or modem design
  • Experience with EDA tools such as HDL simulators (e.g. VCS, Questa, IES), HDL Lint tools (e.g. Spyglass), FPGA tools (e.g. Xilinx Vivado, Altera Quartus II)
  • Experience and understanding of AXI/AHB/APB protocols
  • Strong foundation in electrical engineering fundamentals
  • Experience debugging complex PCBs containing Microprocessors and FPGAs in the lab using equipment such as oscilloscopes and spectrum analyzers
  • Ability to work in a dynamic environment with changing needs and requirements
  • Team-player, can-do attitude and ability to work well in a group environment while still contributing on an individual basis
  • Demonstrated ability to work in a highly cross-functional role
  • Enjoys being challenged and learning new skills
  • Master's in Electrical/Computer Engineering or related field

ADDITIONAL REQUIREMENTS:
  • Ability to work extended hours or weekends as needed for mission critical deadlines

COMPENSATION & BENEFITS:
Pay range:
ASIC Design Engineer/Level I: $125,000.00 - $145,000.00/per year
ASIC Design Engineer/Level II: $140,000.00 - $175,000.00/per year
Your actual level and base salary will be determined on a case-by-case basis and may vary based on the following considerations: job-related knowledge and skills, education, and experience.
Base salary is just one part of your total rewards package at SpaceX. You may also be eligible for long-term incentives, in the form of company stock, stock options, or long-term cash awards, as well as potential discretionary bonuses and the ability to purchase additional stock at a discount through an Employee Stock Purchase Plan. You will also receive access to comprehensive medical, vision, and dental coverage, access to a 401(k) retirement plan, short & long-term disability insurance, life insurance, paid parental leave, and various other discounts and perks. You may also accrue 3 weeks of paid vacation & will be eligible for 10 or more paid holidays per year. Exempt employees are eligible for 5 days of sick leave per year.
ITAR REQUIREMENTS:
  • To conform to U.S. Government export regulations, applicant must be a (i) U.S. citizen or national, (ii) U.S. lawful, permanent resident (aka green card holder), (iii) Refugee under 8 U.S.C. § 1157, or (iv) Asylee under 8 U.S.C. § 1158, or be eligible to obtain the required authorizations from the U.S. Department of State. Learn more about the ITAR here.

SpaceX is an Equal Opportunity Employer; employment with SpaceX is governed on the basis of merit, competence and qualifications and will not be influenced in any manner by race, color, religion, gender, national origin/ethnicity, veteran status, disability status, age, sexual orientation, gender identity, marital status, mental or physical disability or any other legally protected status.
Applicants wishing to view a copy of SpaceX's Affirmative Action Plan for veterans and individuals with disabilities, or applicants requiring reasonable accommodation to the application/interview process should reach out to EEOCompliance@spacex.com.

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