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New Grad Asic Design Verification Engineer Jobs in Seattle, WA

K2 Space

Senior ASIC Design Verification Engineer

Seattle, WA · On-site

$170K - $250K/yr

  • Medical

  • Dental

  • Vision

  • Life

  • PTO

The Role We are seeking a Senior ASIC Design Verification Engineer whose role will be to verify the functionality, performance, and robustness of our custom silicon designs. You will help define the ...

Socket.dev

ASIC Design Verification Engineer

Seattle, WA · On-site

$130 - $200/hr

  • Medical

  • Dental

  • Vision

  • Life

  • PTO

... this new era demands a fundamentally different class of spacecraft. Engineered to survive the ... The Role We are seeking an ASIC Design Verification Engineer whose role will be to verify the ...

K2 Space

Principal ASIC Design Verification Engineer

Seattle, WA · On-site

$190K - $285K/yr

  • Medical

  • Dental

  • Vision

  • Life

  • PTO

... this new era demands a fundamentally different class of spacecraft. Engineered to survive the ... The Role We are seeking a Principal ASIC Design Verification Engineer whose role will be to verify ...

K2 Space

Senior ASIC Design Verification Engineer

Seattle, WA · On-site

$170K - $250K/yr

  • Medical

  • Dental

  • Vision

  • Life

  • PTO

... this new era demands a fundamentally different class of spacecraft. Engineered to survive the ... The Role We are seeking a Senior ASIC Design Verification Engineer whose role will be to verify the ...

Apple

Design Verification Engineer

Seattle, WA

$175K - $308K/yr

  • Medical

  • Dental

  • Retirement

At Apple, our new ideas have a way of becoming great products, services, and customer experiences ... Design Verification Engineers at Apple are responsible for verifying the functionality and ...

Apple

Design Verification Engineer

Seattle, WA

$142K - $263K/yr

  • Medical

  • Dental

  • Retirement

At Apple, our new ideas have a way of becoming great products, services, and customer experiences ... Design Verification Engineers at Apple are responsible for verifying the functionality and ...

Nytec, Inc.

Design Verification Engineer - EE

Redmond, WA · On-site

$152K - $185K/yr

Our large enterprise client is looking for a strong Design Verification Engineer with Electrical ... Develop new and modify existing tests with creative ideas and simplification * Be concise and clear ...

Nytec, Inc.

Design Verification Engineer - EE

Redmond, WA · On-site

$152K - $185K/yr

Our large enterprise client is looking for a strong Design Verification Engineer with Electrical ... Develop new and modify existing tests with creative ideas and simplification * Be concise and clear ...

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All JobsNew Grad Asic Design Verification Engineer JobsNew Grad Asic Design Verification Engineer Jobs in Seattle, WA

New Grad Asic Design Verification Engineer information

See Seattle, WA salary details

$120.1K

$169.7K

$190.1K

How much do new grad asic design verification engineer jobs pay per year?

As of Aug 16, 2026, the average yearly pay for new grad asic design verification engineer in Seattle, WA is $169,736.00, according to ZipRecruiter salary data. Most workers in this role earn between $154,800.00 and $188,900.00 per year, depending on experience, location, and employer.

What does a new grad ASIC design verification engineer do?

A New Grad ASIC Design Verification Engineer is responsible for testing and validating the design of Application-Specific Integrated Circuits (ASICs) to ensure they meet functional and performance specifications. They typically create testbenches, develop verification plans, write test cases using hardware description languages like SystemVerilog, and debug issues found during simulations. This role is crucial for catching design flaws before manufacturing, working closely with design engineers and using both manual and automated verification methods. As a new graduate, you will learn industry-standard verification methodologies and tools while contributing to the success of the silicon development process.

What are the key skills and qualifications needed to thrive as a new grad ASIC design verification engineer?

To thrive as a New Grad ASIC Design Verification Engineer, you need a solid understanding of digital design principles, hardware description languages (such as Verilog or VHDL), and a relevant degree in electrical or computer engineering. Familiarity with industry-standard verification tools and environments like SystemVerilog, UVM, and simulation/debugging platforms is typically required. Strong analytical thinking, attention to detail, and effective teamwork skills help you excel in diagnosing issues and collaborating with design teams. These skills and qualities ensure robust verification processes that lead to functional, reliable ASIC products.

What is the difference between New Grad Asic Design Verification Engineer vs New Grad Digital Design Engineer?

AspectNew Grad Asic Design Verification EngineerNew Grad Digital Design Engineer
Required SkillsHardware verification, simulation, scripting, HDL knowledgeDigital circuit design, HDL coding, logic design
Work EnvironmentVerification labs, simulation tools, hardware testingDesign teams, FPGA/ASIC development, coding
Industry UsagePrimarily in semiconductor and chip companiesBroadly in electronics, semiconductor, and tech firms

While both roles require HDL knowledge and work in semiconductor environments, the New Grad Asic Design Verification Engineer focuses on verifying and testing ASIC designs, whereas the New Grad Digital Design Engineer is involved in designing digital circuits. Both roles are essential in chip development but differ in their primary responsibilities and skill emphasis.

What are some common challenges new graduates face when starting as an ASIC design verification engineer, and how can they overcome them?

New grad ASIC Design Verification Engineers often encounter challenges such as understanding complex verification environments, learning industry-standard tools and methodologies like UVM, and effectively debugging hardware designs. To overcome these, it's helpful to actively seek mentorship from experienced team members, participate in code reviews, and utilize available documentation and training resources. Collaborating closely with designers and verification leads, asking questions, and consistently practicing hands-on simulations can accelerate learning and build confidence in tackling verification tasks.

What are popular job titles related to New Grad Asic Design Verification Engineer jobs in Seattle, WA?

For New Grad Asic Design Verification Engineer jobs in Seattle, WA, the most frequently searched job titles are:

What job categories do people searching New Grad Asic Design Verification Engineer jobs in Seattle, WA look for?

The top searched job categories for New Grad Asic Design Verification Engineer jobs in Seattle, WA are:

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Cities near Seattle, WA with the most New Grad Asic Design Verification Engineer job openings:

New Grad Asic Design Verification Engineer jobs near you
Infographic showing various New Grad Asic Design Verification Engineer job openings in Seattle, WA as of August 2026, with employment types broken down into 87% Full Time, 8% Part Time, and 5% Contract. Highlights an 85% Physical, 4% Hybrid, and 11% Remote job distribution, with an average salary of $169,736 per year, or $81.6 per hour.

Principal ASIC Design Verification Engineer

K2 Space

Seattle, WA

$190K - $285K/yr

Full-time

Medical, Dental, Vision, Life, PTO

Re-posted 16 days ago

Job description

The Role 

We are seeking a Principal ASIC Design Verification Engineer whose role will be to verify the functionality, performance, and robustness of our custom silicon designs. You will help define the verification approach, contribute to methodology, and work closely with architecture, RTL design, DFT, firmware, physical design, and silicon validation engineers. This is a hands-on role with high ownership, deep technical engagement, and the opportunity to shape first-generation silicon. 

Responsibilities 

  • Develop and execute verification plans for block-level, subsystem-level, and full-chip environments.
  • Build SystemVerilog/UVM test benches, including agents, monitors, scoreboards, checkers, and coverage models.
  • Write SystemVerilog Assertions (SVA) and integrate formal verification where appropriate.
  • Drive constrained-random and directed testing strategies to validate functionality, corner cases, and stress scenarios.
  • Run simulations, triage failures, drive root-cause analysis, and collaborate with RTL designers to resolve issues.
  • Implement and maintain functional coverage, code coverage, assertion coverage, and ensure coverage closure for sign-off.
  • Manage regression testing, simulation farms, and CI pipelines to ensure high test throughput and fast debug iterations.
  • Participate in design reviews, microarchitecture discussions, and influence design-for-verification (DFV) best practices.
  • Work closely with architecture, RTL design, DFT, firmware, physical design, and silicon validation engineers to ensure end-to-end coverage and test.
  • Support silicon bring-up and post-silicon validation through test reuse, diagnostics, and debug analysis.
  • Participate in ASIC team interviews.
  • Drive advancement of DV methodologies and improvements.
  • Manage external IP providers and verification partners when needed.
  • Take lead on large and/or complex systems. 

Qualifications 

  • B.S. or M.S. in Electrical Engineering, Computer Engineering, or related field.
  • 10+ years of experience in ASIC/SoC verification.
  • Solid understanding of SystemVerilog, digital logic, RTL design, DFT, and hardware design and verification flows.
  • Proficiency with several simulation (VCS, Xcelium, Questa), waveform debug (Verdi, SimVision), coverage tools, and scripting languages (ex: Python, Perl, TCL).
  • Experience with test planning, UVM-based testbench development, constrained-random testing, functional coverage, and SystemVerilog assertions.
  • Experience with regression management, coverage analysis, revision control (ex: Git), CI/CD automation, and gate-level simulation.
  • Experience with developing and integrating reference models.
  • Experience with embedded processor-based designs and firmware/bare metal coding (ex: C, C++).
  • Understanding of many industry-standard interfaces (ex: APB/AHB/AXI).
  • Involvement in post-silicon validation planning and execution. 

Nice to Have

  • Experience with low power verification.
  • Experience with analog behavioral models.
  • Familiarity with physical design flows.
  • Experience working in cross-functional, geographically distributed teams.
  • Experience in space, telecom, or RF/digital mixed systems is a plus. 

Compensation and Benefits:

  • Base salary range for this role is $190,000 - $285,000 + equity in the company
  • Salary will be based on several factors including, but not limited to: knowledge and skills, education, and experience level
  • Comprehensive benefits package including paid time off, medical/dental/vision/ coverage, life insurance, paid parental leave, and many other perks
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About K2 Space

Sourced by ZipRecruiter

Industry

Guided missile and space vehicle manufacturing

Company size

11 - 50 Employees

Headquarters location

Los Angeles, CA, US

Year founded

2022

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