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New Grad Asic Design Verification Engineer Jobs (NOW HIRING)

Cisco

ASIC Design Verification Engineer

San Jose, CA · On-site

$152.50K - $219.20K/yr

Your Impact As an ASIC Design Verification Engineer, you will play a critical role in developing ... New York City Metro Area: $152,500.00 - $252,000.00 Non-Metro New York state & Washington state ...

Cisco

ASIC Design Verification Engineer

San Jose, CA · On-site

$152.50K - $219.20K/yr

Your Impact As an ASIC Design Verification Engineer, you will play a critical role in developing ... New York City Metro Area: $152,500.00 - $252,000.00 Non-Metro New York state & Washington state ...

K2 Space

OR

$130K - $200K/yr

The Role We are seeking an ASIC Design Verification Engineer whose role will be to verify the functionality, performance, and robustness of our custom silicon designs. You will help define the ...

Broadcom, Inc.

ASIC Verification Engineer

Irvine, CA · On-site

$91K - $146K/yr

MSEE/CS (New Grad) OR BSEE/CS with 3+ years of direct ASIC Design/Verification experience. * Core Fundamentals: Strong grasp of logic design, computer architecture and networking protocols.

Ericsson

ASIC Design Verification Engineer

Austin, TX · On-site

$134.80K - $164.50K/yr

ASIC Design Verification Engineer Austin, Texas This is not a remote work opportunity Hybrid work ... New employees are provided a minimum of 15 days of accrued vacation, up to 3 personal days per year ...

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New Grad Asic Design Verification Engineer information

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$105.5K

$149.2K

$167K

How much do new grad asic design verification engineer jobs pay per year?

As of May 29, 2026, the average yearly pay for new grad asic design verification engineer in the United States is $149,150.00, according to ZipRecruiter salary data. Most workers in this role earn between $136,000.00 and $166,000.00 per year, depending on experience, location, and employer.

What are the key skills and qualifications needed to thrive as a New Grad ASIC Design Verification Engineer, and why are they important?

To thrive as a New Grad ASIC Design Verification Engineer, you need a solid understanding of digital design principles, hardware description languages (such as Verilog or VHDL), and a relevant degree in electrical or computer engineering. Familiarity with industry-standard verification tools and environments like SystemVerilog, UVM, and simulation/debugging platforms is typically required. Strong analytical thinking, attention to detail, and effective teamwork skills help you excel in diagnosing issues and collaborating with design teams. These skills and qualities ensure robust verification processes that lead to functional, reliable ASIC products.

What are some common challenges new graduates face when starting as an ASIC Design Verification Engineer, and how can they overcome them?

New grad ASIC Design Verification Engineers often encounter challenges such as understanding complex verification environments, learning industry-standard tools and methodologies like UVM, and effectively debugging hardware designs. To overcome these, it's helpful to actively seek mentorship from experienced team members, participate in code reviews, and utilize available documentation and training resources. Collaborating closely with designers and verification leads, asking questions, and consistently practicing hands-on simulations can accelerate learning and build confidence in tackling verification tasks.

What does a New Grad ASIC Design Verification Engineer do?

A New Grad ASIC Design Verification Engineer is responsible for testing and validating the design of Application-Specific Integrated Circuits (ASICs) to ensure they meet functional and performance specifications. They typically create testbenches, develop verification plans, write test cases using hardware description languages like SystemVerilog, and debug issues found during simulations. This role is crucial for catching design flaws before manufacturing, working closely with design engineers and using both manual and automated verification methods. As a new graduate, you will learn industry-standard verification methodologies and tools while contributing to the success of the silicon development process.

What is the difference between New Grad Asic Design Verification Engineer vs New Grad Digital Design Engineer?

AspectNew Grad Asic Design Verification EngineerNew Grad Digital Design Engineer
Required SkillsHardware verification, simulation, scripting, HDL knowledgeDigital circuit design, HDL coding, logic design
Work EnvironmentVerification labs, simulation tools, hardware testingDesign teams, FPGA/ASIC development, coding
Industry UsagePrimarily in semiconductor and chip companiesBroadly in electronics, semiconductor, and tech firms

While both roles require HDL knowledge and work in semiconductor environments, the New Grad Asic Design Verification Engineer focuses on verifying and testing ASIC designs, whereas the New Grad Digital Design Engineer is involved in designing digital circuits. Both roles are essential in chip development but differ in their primary responsibilities and skill emphasis.

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New Grad Asic Design Verification Engineer jobs near you
Infographic showing various New Grad Asic Design Verification Engineer job openings in the United States as of May 2026, with employment types broken down into 90% Full Time, 5% Part Time, and 5% Contract. Highlights an 12% Physical, 1% Hybrid, and 87% Remote job distribution, with an average salary of $149,150 per year, or $71.7 per hour.
Sr. ASIC Design Verification Engineer (Starshield)

Sr. ASIC Design Verification Engineer (Starshield)

SpaceX

Irvine, CA

$160K - $225K/yr

Other

Medical, Dental, Vision, Life, Retirement, PTO

Posted 25 days ago

SpaceX rating

8.7

Company rating: 8.7 out of 10

Based on 142 frontline employees who took The Breakroom Quiz

12th of 59 rated aerospace companies

Job description

SR. ASIC DESIGN VERIFICATION ENGINEER (STARSHIELD)

Starshield leverages SpaceX's Starlink technology and launch capability to support national security efforts. While Starlink is designed for consumer and commercial use, Starshield is designed for government use, with an initial focus on earth observation, communications, and hosted payloads. As an ASIC Design Verification Engineer on the Starshield team, you will be working on advanced development programs in support of U.S. National Security. In this role, you will be developing cutting-edge next-generation FPGAs and ASICs for deployment in space and ground infrastructures around the globe. You will work in a highly collaborative and fast-paced environment, where we are exploring unsolved problems and applying the SpaceX mindset of iterating rapidly to go from design and demo to operational capability at lightning pace.

RESPONSIBILITIES:

  • Responsible for digital ASIC verification at block and system level
  • Lead and execute verification test plan, development, and milestones from beginning to end, develop test harnesses and test sequences
  • Develop SystemVerilog testbench infrastructure (both UVM and non-UVM) for testing designs, including DSP blocks
  • Responsible for test plan execution, running regressions, code and functional coverage closure
  • Automate test case generation by using Python and MATLAB programs
  • Contribute to pre-silicon verification, chip bring-up and post-silicon validation
  • Be a hands-on self-starter who can execute the steps required to fully verify complex digital designs

BASIC QUALIFICATIONS:

  • Bachelor's degree in electrical engineering, computer engineering, or computer science
  • 5+ years of experience with design verification and test bench development

PREFERRED SKILLS AND EXPERIENCE:

  • Advanced degree in electrical engineering or computer engineering
  • Experience with verification methodologies such as UVM/OVM/VMM
  • Strong object-oriented programming knowledge
  • Strong problem-solving and coding skills
  • Experience in constrained random verification
  • Expertise in developing test plans, implementing coverage models, and analyzing results
  • Experience with scripting languages, e.g. Python for automation
  • RTL design, chip bring-up, and post-silicon validation experience
  • Ability to work in a dynamic environment with changing needs and requirements
  • Ability to work in a dynamic environment with changing needs and requirements
  • Team-player, can-do attitude and ability to work well in a group environment while still contributing on an individual basis
  • Enjoy being challenged and learning new skills

ADDITIONAL REQUIREMENTS:

  • Ability to work long hours and weekends as necessary to support critical milestones
  • Willingness to travel for off-site testing
  • An active clearance may provide the opportunity for you to work on sensitive SpaceX missions; if so, you will be subject to pre-employment drug and random drug and alcohol testing

COMPENSATION AND BENEFITS:    
Pay range:    
Sr. ASIC Design Verification Engineer: $160,000.00 - $225,000.00/per year    
Your actual level and base salary will be determined on a case-by-case basis and may vary based on the following considerations: job-related knowledge and skills, education, and experience. Those with an active clearance will receive a 10% differential, up to an additional $15,000 annually, once officially briefed into a classified program.

Base salary is just one part of your total rewards package at SpaceX. You may also be eligible for long-term incentives, in the form of company stock, stock options, or long-term cash awards, as well as potential discretionary bonuses and the ability to purchase additional stock at a discount through an Employee Stock Purchase Plan. You will also receive access to comprehensive medical, vision, and dental coverage, access to a 401(k) retirement plan, short and long-term disability insurance, life insurance, paid parental leave, and various other discounts and perks. You may also accrue 3 weeks of paid vacation and will be eligible for 10 or more paid holidays per year. Employees accrue paid sick leave pursuant to Company policy which satisfies or exceeds the accrual, carryover, and use requirements of the law.

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