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New Grad Asic Design Verification Engineer Jobs in California

Cisco

ASIC Design Verification Engineer

San Jose, CA · On-site

$155K - $222K/yr

Your Impact As an ASIC Design Verification Engineer, you will play a critical role in developing ... New York City Metro Area: $155,000.00 - $256,000.00 Non-Metro New York state & Washington state ...

Meta

ASIC Engineer, Design Verification

Sunnyvale, CA · On-site +1

$146K/yr

Meta is hiring ASIC Design Verification Engineer within the Infrastructure organization. We are looking for individuals with experience in Design Verification to build IP and System On Chip (SoC) for ...

Meta

ASIC Engineer, Design Verification

Sunnyvale, CA

$114K/yr

Meta is hiring ASIC Design Verification Engineer within the Infrastructure organization. We are looking for individuals with experience in Design Verification to build IP and System On Chip (SoC) for ...

Cisco

ASIC Design Verification Engineer

San Jose, CA · On-site

$165K - $241K/yr

Influence ASIC architecture and design to enable robust verification and high-quality silicon ... Serve as subject matter expert and advisor on industry trends, best practices, and new technologies.

Cisco

ASIC Design Verification Engineer

San Jose, CA · On-site

$165K - $241K/yr

Participate in the ASIC design verification for Cisco high-end switching products. * Perform end-to ... New York City Metro Area: $165,000.00 - $277,600.00 Non-Metro New York state & Washington state ...

Cisco

ASIC Design Verification Engineer

San Jose, CA · On-site

$152K - $219K/yr

Your Impact As an ASIC Design Verification Engineer, you will play a critical role in developing ... New York City Metro Area: $152,500.00 - $252,000.00 Non-Metro New York state & Washington state ...

Qualcomm

ASIC Design Verification Engineer

Santa Clara, CA · On-site

$107K - $161K/yr

As a Qualcomm ASIC Engineer, you will define, model, design (digital and/or analog), optimize, verify, validate, implement, and document IP (block/SoC) development for a variety of high performance ...

Cisco

ASIC Design Verification Engineer

San Jose, CA · On-site

$152K - $219K/yr

Your Impact As an ASIC Design Verification Engineer, you will play a critical role in developing ... New York City Metro Area: $152,500.00 - $252,000.00 Non-Metro New York state & Washington state ...

Cisco

ASIC Design Verification Engineer

San Jose, CA · On-site

$165K - $241K/yr

Participate in the ASIC design verification for Cisco high-end switching products. * Perform end-to ... New York City Metro Area: $165,000.00 - $277,600.00 Non-Metro New York state & Washington state ...

Meta

ASIC Engineer, Design Verification

Sunnyvale, CA · On-site +1

$114K/yr

Meta is hiring an ASIC Design Verification Engineer within the Infrastructure Silicon organization. We are looking for individuals with experience in Design Verification to build IP and System on ...

Cisco

ASIC Design Verification Engineer

San Jose, CA · On-site

$165K - $241K/yr

Influence ASIC architecture and design to enable robust verification and high-quality silicon ... Serve as subject matter expert and advisor on industry trends, best practices, and new technologies.

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All JobsNew Grad Asic Design Verification Engineer JobsNew Grad Asic Design Verification Engineer Jobs in California

New Grad Asic Design Verification Engineer information

What does a new grad ASIC design verification engineer do?

A New Grad ASIC Design Verification Engineer is responsible for testing and validating the design of Application-Specific Integrated Circuits (ASICs) to ensure they meet functional and performance specifications. They typically create testbenches, develop verification plans, write test cases using hardware description languages like SystemVerilog, and debug issues found during simulations. This role is crucial for catching design flaws before manufacturing, working closely with design engineers and using both manual and automated verification methods. As a new graduate, you will learn industry-standard verification methodologies and tools while contributing to the success of the silicon development process.

What are the key skills and qualifications needed to thrive as a new grad ASIC design verification engineer?

To thrive as a New Grad ASIC Design Verification Engineer, you need a solid understanding of digital design principles, hardware description languages (such as Verilog or VHDL), and a relevant degree in electrical or computer engineering. Familiarity with industry-standard verification tools and environments like SystemVerilog, UVM, and simulation/debugging platforms is typically required. Strong analytical thinking, attention to detail, and effective teamwork skills help you excel in diagnosing issues and collaborating with design teams. These skills and qualities ensure robust verification processes that lead to functional, reliable ASIC products.

What is the difference between New Grad Asic Design Verification Engineer vs New Grad Digital Design Engineer?

AspectNew Grad Asic Design Verification EngineerNew Grad Digital Design Engineer
Required SkillsHardware verification, simulation, scripting, HDL knowledgeDigital circuit design, HDL coding, logic design
Work EnvironmentVerification labs, simulation tools, hardware testingDesign teams, FPGA/ASIC development, coding
Industry UsagePrimarily in semiconductor and chip companiesBroadly in electronics, semiconductor, and tech firms

While both roles require HDL knowledge and work in semiconductor environments, the New Grad Asic Design Verification Engineer focuses on verifying and testing ASIC designs, whereas the New Grad Digital Design Engineer is involved in designing digital circuits. Both roles are essential in chip development but differ in their primary responsibilities and skill emphasis.

What are some common challenges new graduates face when starting as an ASIC design verification engineer, and how can they overcome them?

New grad ASIC Design Verification Engineers often encounter challenges such as understanding complex verification environments, learning industry-standard tools and methodologies like UVM, and effectively debugging hardware designs. To overcome these, it's helpful to actively seek mentorship from experienced team members, participate in code reviews, and utilize available documentation and training resources. Collaborating closely with designers and verification leads, asking questions, and consistently practicing hands-on simulations can accelerate learning and build confidence in tackling verification tasks.
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Infographic showing various New Grad Asic Design Verification Engineer job openings in California as of August 2026, with employment types broken down into 87% Full Time, 8% Part Time, and 5% Contract. Highlights an 85% Physical, 4% Hybrid, and 11% Remote job distribution.

ASIC Engineer, Design Verification

Meta

Sunnyvale, CA

Full-time

Re-posted 7 days ago

Meta rating

7.8

Company rating: 7.8 out of 10

Based on 45 frontline employees who took The Breakroom Quiz

136th of 242 rated software companies

Job description

Meta is hiring ASIC Design Verification Engineer within the Infrastructure organization. We are looking for individuals with experience in Design Verifi...

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