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Asic Dft Engineer Jobs in California (NOW HIRING)

Purple Hires Inc

ASIC DFT Engineer

Irvine, CA · On-site

... ASIC DFT Engineer to architect, implement, verify, and debug advanced DFT solutions for complex ASIC and SoC designs. This role requires deep technical ownership across DFT architecture, scan ...

Vkore Solutions

Lead ASIC DFT Engineer

San Jose, CA · On-site

Role: Lead ASIC DFT Engineer Location: Remote Experience 10+ years of hands-on experience in ASIC Design-for-Test (DFT) Role Summary We are seeking a highly experienced Lead ASIC DFT Engineer to ...

Broadcom

ASIC DFT Engineer

San Jose, CA · On-site

Broadcom's ASIC Product Division (APD) is seeking candidates for a DFT position at ourSan Jose ... Working closely with STA and DI Engineers design closure for test * Generating, verifying, and ...

Broadcom

ASIC DFT Engineer

San Jose, CA · On-site

$141K - $226K/yr

Broadcom's ASIC Product Division (APD) is seeking candidates for a DFT position at ourSan Jose ... Working closely with STA and DI Engineers design closure for test * Generating, Verifying ...

Cisco

ASIC DFT Engineer

San Jose, CA

$165K - $241K/yr

You will be in the Silicon One development organization as an ASIC DFT Engineer . You will work with Front-end RTL teams, backend physical design teams to understand chip architecture and drive DFT ...

Cisco

ASIC DFT Engineer

San Jose, CA · On-site

$165K - $241K/yr

You will be in the Silicon One development organization as an ASIC DFT Engineer . You will work with Front-end RTL teams, backend physical design teams to understand chip architecture and drive DFT ...

Cisco

ASIC DFT Engineer

San Jose, CA · On-site

$152K - $219K/yr

... ASIC Engineer, with a primary focus on Design-for-Test. You will work with Front-end RTL teams, backend physical design teams to understand chip architecture and drive DFT requirements early in the ...

SpaceX

Sr. ASIC DFT Engineer (Silicon)

Palo Alto, CA · On-site

$175K - $280K/yr

SR. ASIC DFT ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience in building rockets and spacecraft to deploy Starlink, the world's most advanced broadband internet system.

SpaceX

Sr. ASIC DFT Engineer (Silicon)

Palo Alto, CA · On-site

$175K - $280K/yr

Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars. SR. ASIC DFT ENGINEER (SILICON ENGINEERING) At SpaceX we're ...

Cisco

ASIC DFT Engineer

San Jose, CA

$152K - $219K/yr

... ASIC Engineer, with a primary focus on Design-for-Test. You will work with Front-end RTL teams, backend physical design teams to understand chip architecture and drive DFT requirements early in the ...

SpaceX

Sr. ASIC DFT Engineer (Silicon)

Irvine, CA · On-site

$165K - $260K/yr

Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars. SR. ASIC DFT ENGINEER (SILICON ENGINEERING) At SpaceX we're ...

SpaceX

Sr. ASIC DFT Engineer (Silicon)

Irvine, CA · On-site

$165K - $260K/yr

Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars. SR. ASIC DFT ENGINEER (SILICON ENGINEERING) At SpaceX we're ...

SpaceX

Sr. ASIC DFT Engineer (Silicon)

Irvine, CA · On-site

$165K - $260K/yr

SR. ASIC DFT ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience in building rockets and spacecraft to deploy Starlink, the world's most advanced broadband internet system.

SpaceX

Sr. ASIC DFT Engineer (Silicon)

Palo Alto, CA · On-site

$175K - $280K/yr

Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars. SR. ASIC DFT ENGINEER (SILICON ENGINEERING) At SpaceX we're ...

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All JobsAsic Dft Engineer JobsAsic Dft Engineer Jobs in California

Asic Dft Engineer information

What is the difference between Asic Dft Engineer vs Asic Verification Engineer?

AspectAsic Dft EngineerAsic Verification Engineer
Primary FocusDesign for Testability (DFT) implementation and validationFunctional verification of ASIC designs
Skills & CertificationsRTL design, DFT tools, scripting languagesHardware description languages, verification methodologies
Work EnvironmentDesign teams, DFT tool suitesVerification environments, simulation tools
Industry UsageSemiconductor, electronics manufacturingSemiconductor, electronics design companies

While both roles are integral to ASIC development, Asic Dft Engineers focus on ensuring designs are testable and manufacturable, whereas Asic Verification Engineers concentrate on verifying the correctness of the design before fabrication.

What are popular job titles related to Asic Dft Engineer jobs in California? For Asic Dft Engineer jobs in California, the most frequently searched job titles are:
What job categories do people searching Asic Dft Engineer jobs in California look for? The top searched job categories for Asic Dft Engineer jobs in California are:
What cities in California are hiring for Asic Dft Engineer jobs? Cities in California with the most Asic Dft Engineer job openings:
Asic Dft Engineer jobs near you
Infographic showing various Asic Dft Engineer job openings in California as of August 2026, with employment types broken down into 87% Full Time, and 13% Contract. Highlights an 94% In-person, 2% Hybrid, and 4% Remote job distribution.

ASIC DFT Engineer

Purple Hires Inc

Irvine, CA • On-site

Contractor

Re-posted 6 days ago

Job description

Job Description

Key skills for Lead ASIC DFT:

 

please see these key words of in the project description for the profile consideration.

  “SCAN, ATPG, MBIST, Timing Simulations,  SDF, SDC ,  PSV, Diagnosys ,  Pattern Retargeting , Pattern porting,  DRCs,  TetraMax, DFTMax “

Experience

10+ years of hands-on experience in ASIC Design-for-Test (DFT)

Role Summary

We are seeking a highly experienced Lead ASIC DFT Engineer to architect, implement, verify, and debug advanced DFT solutions for complex ASIC and SoC designs. This role requires deep technical ownership across DFT architecture, scan insertion, ATPG, MBIST/LBIST, JTAG, boundary scan, and post-silicon validation, along with the ability to lead cross-functional debug efforts and drive resolution of critical silicon issues.

The ideal candidate will have strong hands-on expertise in DFT fundamentals, fault models, test coverage, diagnosis, and debug, as well as the ability to evaluate and adopt emerging DFT methodologies and architecture schemes to improve robustness, quality, and yield.

Key Responsibilities

  • Lead DFT architecture, implementation, verification, and sign-off for complex ASIC and SoC designs.
  • Drive scan architecture, scan insertion, scan chain stitching, and scan compression workflows to achieve high coverage and robust testability.
  • Own MBIST/LBIST integration, implementation, verification, and debug across design and silicon bring-up phases.
  • Perform DFT debug, failure analysis, root-cause investigation, and fault coverage closure for complex silicon issues.
  • Develop and validate DFT constraints, including DFT SDC, timing checks, and DFT-specific timing analysis.
  • Collaborate with RTL design, verification, physical design, STA, and silicon validation teams to resolve integration and implementation issues.
  • Support ATPG pattern generation, ATPG simulations, DRC analysis, test coverage analysis, and diagnosis/debug.
  • Work on JTAG, boundary scan, iJTAG, SSN, and IP-level DFT integration.
  • Review RTL, synthesis, LEC, and physical design impacts on DFT implementation and test quality.
  • Act as a technical escalation point for advanced DFT and post-silicon debug issues.
  • Mentor junior and mid-level DFT engineers and promote best practices in DFT methodology and automation.
  • Develop scripts and automation using TCL, PERL, or Python to improve flow efficiency and debug productivity.

Required Skills & Qualifications

  • Strong hands-on experience in ASIC DFT with end-to-end ownership.
  • Solid understanding of DFT fundamentals, fault models, test techniques, and test coverage concepts.
  • Deep expertise in scan architecture, ATPG, MBIST, LBIST, JTAG, boundary scan, and silicon debug.
  • Hands-on experience with Synopsys, Cadence, and Siemens/Mentor EDA tools.
  • Proven experience in scan insertion, ATPG setup, simulation, debug, and DRC analysis.
  • Experience with MBIST implementation and verification; SMS experience preferred.
  • Experience with scan architecture and scan chain stitching; Tessent/SSN experience preferred.
  • Strong understanding of PLLs, RTL design, synthesis flows, logical equivalence checking (LEC), and physical design implementation.
  • Proven post-silicon debug and silicon bring-up experience.
  • Exposure to large SoC designs, hierarchical DFT flows, and multi-domain integration challenges.
  • Strong communication skills and the ability to work independently with minimal ramp-up.

Preferred Experience

  • MBIST post-silicon validation.
  • ATPG simulations and fault coverage debug.
  • DFT RTL, DFD, DFT verification, and IP-level DFT integration.
  • DFT SDC creation and DFT timing closure support.
  • Boundary scan, iJTAG, SSN, and design-for-debug methodologies.
  • TCL/PERL scripting for DFT automation, reporting, and debug.
  • Experience working across multiple ASIC technology nodes and complex product development cycles.
  • Familiarity with yield learning, diagnosis, and manufacturing test optimization.