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Asic Dft Engineer Jobs (NOW HIRING)

Purple Hires Inc

ASIC DFT Engineer

Plano, TX · Remote

Lead ASIC DFT Engineer Location: Remote, (Onsite) Duration: Contract Year of Exp: 8+ yrs to 15 yrs. We are seeking a highly experienced Lead ASIC DFT Engineer to architect, implement, verify, and ...

Purple Hires Inc

ASIC DFT Engineer

Irvine, CA · On-site

... ASIC DFT Engineer to architect, implement, verify, and debug advanced DFT solutions for complex ASIC and SoC designs. This role requires deep technical ownership across DFT architecture, scan ...

Tanisha Systems, Inc.

ASIC DFT Engineer

Rockford, IL · On-site

Title - Lead ASIC DFT Engineer Location - Remote (must be aligned with PST time zone) Type :- */W2 Experience 10+ years of hands-on experience in ASIC Design-for-Test (DFT) Role Summary We are ...

Vkore Solutions

Lead ASIC DFT Engineer

San Jose, CA · On-site

Role: Lead ASIC DFT Engineer Location: Remote Experience 10+ years of hands-on experience in ASIC Design-for-Test (DFT) Role Summary We are seeking a highly experienced Lead ASIC DFT Engineer to ...

Purple Hires Inc

Lead ASIC DFT Engineer

San Jose, CA · Remote

Title - Lead ASIC DFT Engineer Location - Remote (must be aligned with PST time zone) Below is the detailed for your reference - Experience 10+ years of hands-on experience in ASIC Design-for-Test ...

Purple Hires Inc

Lead ASIC DFT Engineer

Plano, TX · Remote

... ASIC DFT Engineer to architect, implement, verify, and debug advanced DFT solutions for complex ASIC and SoC designs. This role requires deep technical ownership across DFT architecture, scan ...

Broadcom, Inc.

ASIC DFT Engineer

San Jose, CA · On-site

$141K - $226K/yr

Broadcom's ASIC Product Division (APD) is seeking candidates for a DFT position at our San Jose ... Working closely with STA and DI Engineers design closure for test * Generating, verifying, and ...

Broadcom

ASIC DFT Engineer

San Jose, CA

$141K - $226K/yr

Broadcom's ASIC Product Division (APD) is seeking candidates for a DFT position at ourSan Jose ... Working closely with STA and DI Engineers design closure for test * Generating, verifying, and ...

Broadcom, Inc.

ASIC DFT Engineer

San Jose, CA · On-site

$141K - $226K/yr

Broadcom's ASIC Product Division (APD) is seeking candidates for a DFT position at our San Jose ... Working closely with STA and DI Engineers design closure for test * Generating, Verifying ...

Broadcom

ASIC DFT Engineer

San Jose, CA · On-site

$141K - $226K/yr

Broadcom's ASIC Product Division (APD) is seeking candidates for a DFT position at ourSan Jose ... Working closely with STA and DI Engineers design closure for test * Generating, Verifying ...

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All JobsAsic Dft Engineer Jobs

Asic Dft Engineer information

See salary details

$82.5K

$158.2K

$167.5K

How much do asic dft engineer jobs pay per year?

As of Jul 18, 2026, the average yearly pay for asic dft engineer in the United States is $158,244.00, according to ZipRecruiter salary data. Most workers in this role earn between $166,000.00 and $166,000.00 per year, depending on experience, location, and employer.

What is the difference between Asic Dft Engineer vs Asic Verification Engineer?

AspectAsic Dft EngineerAsic Verification Engineer
Primary FocusDesign for Testability (DFT) implementation and validationFunctional verification of ASIC designs
Skills & CertificationsRTL design, DFT tools, scripting languagesHardware description languages, verification methodologies
Work EnvironmentDesign teams, DFT tool suitesVerification environments, simulation tools
Industry UsageSemiconductor, electronics manufacturingSemiconductor, electronics design companies

While both roles are integral to ASIC development, Asic Dft Engineers focus on ensuring designs are testable and manufacturable, whereas Asic Verification Engineers concentrate on verifying the correctness of the design before fabrication.

More about Asic Dft Engineer jobs
What cities are hiring for Asic Dft Engineer jobs? Cities with the most Asic Dft Engineer job openings:
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Asic Dft Engineer jobs near you
Infographic showing various Asic Dft Engineer job openings in the United States as of July 2026, with employment types broken down into 97% Full Time, 1% Part Time, and 2% Contract. Highlights an 89% Physical, 6% Hybrid, and 5% Remote job distribution, with an average salary of $158,244 per year, or $76.1 per hour.

ASIC DFT Engineer

Purple Hires Inc

Plano, TX • Remote

Contractor

Posted 21 days ago

Job description

Role: Lead ASIC DFT Engineer
Location: Remote, (Onsite)
Duration: Contract
Year of Exp: 8+ yrs to 15 yrs.
Job Description:
We are seeking a highly experienced Lead ASIC DFT Engineer to architect, implement, verify, and debug advanced DFT solutions for complex ASIC and SoC designs. This role requires deep technical ownership across DFT architecture, scan insertion, ATPG, MBIST/LBIST, JTAG, boundary scan, and post-silicon validation, along with the ability to lead cross-functional debug efforts and drive resolution of critical silicon issues. The ideal candidate will have strong hands-on expertise in DFT fundamentals, fault models, test coverage, diagnosis, and debug, as well as the ability to evaluate and adopt emerging DFT methodologies and architecture schemes to improve robustness, quality, and yield.
Key Responsibilities:
  • Lead DFT architecture, implementation, verification, and sign-off for complex ASIC and SoC designs.
  • Drive scan architecture, scan insertion, scan chain stitching, and scan compression workflows to achieve high coverage and robust testability.
  • Own MBIST/LBIST integration, implementation, verification, and debug across design and silicon bring-up phases.
  • Perform DFT debug, failure analysis, root-cause investigation, and fault coverage closure for complex silicon issues.
  • Develop and validate DFT constraints, including DFT SDC, timing checks, and DFT-specific timing analysis.
  • Collaborate with RTL design, verification, physical design, STA, and silicon validation teams to resolve integration and implementation issues.
  • Support ATPG pattern generation, ATPG simulations, DRC analysis, test coverage analysis, and diagnosis/debug.
  • Work on JTAG, boundary scan, iJTAG, SSN, and IP-level DFT integration.
  • Review RTL, synthesis, LEC, and physical design impacts on DFT implementation and test quality.
  • Act as a technical escalation point for advanced DFT and post-silicon debug issues.
  • Mentor junior and mid-level DFT engineers and promote best practices in DFT methodology and automation.
  • Develop scripts and automation using TCL, PERL, or Python to improve flow efficiency and debug productivity.
Required Skills & Qualifications:
  • Strong hands-on experience in ASIC DFT with end-to-end ownership.
  • Solid understanding of DFT fundamentals, fault models, test techniques, and test coverage concepts.
  • Deep expertise in scan architecture, ATPG, MBIST, LBIST, JTAG, boundary scan, and silicon debug.
  • Hands-on experience with Synopsys, Cadence, and Siemens/Mentor EDA tools.
  • Proven experience in scan insertion, ATPG setup, simulation, debug, and DRC analysis.
  • Experience with MBIST implementation and verification; SMS experience preferred.
  • Experience with scan architecture and scan chain stitching; Tessent/SSN experience preferred.
  • Strong understanding of PLLs, RTL design, synthesis flows, logical equivalence checking (LEC), and physical design implementation.
  • Proven post-silicon debug and silicon bring-up experience.
  • Exposure to large SoC designs, hierarchical DFT flows, and multi-domain integration challenges.
  • Strong communication skills and the ability to work independently with minimal ramp-up.
Preferred Experience:
  • MBIST post-silicon validation.
  • ATPG simulations and fault coverage debug.
  • DFT RTL, DFD, DFT verification, and IP-level DFT integration.
  • DFT SDC creation and DFT timing closure support.
  • Boundary scan, iJTAG, SSN, and design-for-debug methodologies.
  • TCL/PERL scripting for DFT automation, reporting, and debug.
  • Experience working across multiple ASIC technology nodes and complex product development cycles.
  • Familiarity with yield learning, diagnosis, and manufacturing test optimization.