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Asic Dft Engineer Jobs (NOW HIRING)

Broadcom

ASIC DFT Engineer

Fort Collins, CO

$108K - $172.80K/yr

... P DFT integration * Candidate's primary responsibilities will be to verify and validate HBM & Die2Die IP's at ASIC level * Working closely with STA and DI Engineers design closure for test

Broadcom, Inc.

ASIC DFT Engineer

Fort Collins, CO · On-site

$108K - $172.80K/yr

... P DFT integration * Candidate's primary responsibilities will be to verify and validate HBM & Die2Die IP's at ASIC level * Working closely with STA and DI Engineers design closure for test

Broadcom

ASIC DFT Engineer

Fort Collins, CO

$108K - $172.80K/yr

Broadcom's ASIC Product Division (APD) is seeking candidates for a DFT position at ourFort Collins ... Working closely with STA and DI Engineers design closure for test * Generating, Verifying ...

Broadcom, Inc.

ASIC DFT Engineer

San Jose, CA · On-site

$141.30K - $226K/yr

Broadcom's ASIC Product Division (APD) is seeking candidates for a DFT position at our San Jose ... Working closely with STA and DI Engineers design closure for test * Generating, Verifying ...

Broadcom, Inc.

ASIC DFT Engineer

Fort Collins, CO · On-site

$108K - $172.80K/yr

Broadcom's ASIC Product Division (APD) is seeking candidates for a DFT position at our Fort Collins ... Working closely with STA and DI Engineers design closure for test * Generating, Verifying ...

Broadcom, Inc.

ASIC DFT Engineer

San Jose, CA · On-site

$141.30K - $226K/yr

Broadcom's ASIC Product Division (APD) is seeking candidates for a DFT position at our San Jose ... Working closely with STA and DI Engineers design closure for test * Generating, verifying, and ...

Broadcom

ASIC DFT Engineer

San Jose, CA

$141.30K - $226K/yr

Broadcom's ASIC Product Division (APD) is seeking candidates for a DFT position at ourSan Jose ... Working closely with STA and DI Engineers design closure for test * Generating, verifying, and ...

USM

JB061568 - Lead ASIC DFT Engineer

San Jose, CA · On-site

$194.60K/yr

Skills ASIC DFT, Visa Types Green Card, US Citiz.. Required Skills & Qualifications * Strong hands-on experience in ASIC DFT with end-to-end ownership. * Solid understanding of DFT fundamentals ...

Broadcom, Inc.

DFT Engineer

San Jose, CA · On-site

$141.30K - $226K/yr

Principal DFT Engineer Broadcom's ASIC Product Division is seeking candidates for a DFT position at our San Jose, California, Development Center. The successful candidate will be responsible for ...

Sivaltech

DFT Engineer

San Diego, CA

Company Description Sivaltech is a leading design services company with expertise in ASIC/FPGA ... Role Description Sivaltech is seeking a highly skilled and experienced Senior DFT Engineer for a ...

Broadcom, Inc.

DFT Engineer

San Jose, CA · On-site

$81K - $130K/yr

Broadcom's ASIC Product Division is seeking candidates for a DFT position at our San Jose ... Bachelors in Electrical/Electronic/Computer Engineering and 2+ years of relevant industry ...

Intel

DFT Application Engineer

Santa Clara, CA · On-site

Drive quality improvements in ASIC DFT/DFM and ATPG validation methodology, capability/flow, and ... Bachelor's degree in Electrical Engineering, Computer Engineering, or STEM-related field * 3+ years ...

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Asic Dft Engineer information

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$82.5K

$158.2K

$167.5K

How much do asic dft engineer jobs pay per year?

As of May 28, 2026, the average yearly pay for asic dft engineer in the United States is $158,244.00, according to ZipRecruiter salary data. Most workers in this role earn between $166,000.00 and $166,000.00 per year, depending on experience, location, and employer.

What is the difference between Asic Dft Engineer vs Asic Verification Engineer?

AspectAsic Dft EngineerAsic Verification Engineer
Primary FocusDesign for Testability (DFT) implementation and validationFunctional verification of ASIC designs
Skills & CertificationsRTL design, DFT tools, scripting languagesHardware description languages, verification methodologies
Work EnvironmentDesign teams, DFT tool suitesVerification environments, simulation tools
Industry UsageSemiconductor, electronics manufacturingSemiconductor, electronics design companies

While both roles are integral to ASIC development, Asic Dft Engineers focus on ensuring designs are testable and manufacturable, whereas Asic Verification Engineers concentrate on verifying the correctness of the design before fabrication.

More about Asic Dft Engineer jobs
What cities are hiring for Asic Dft Engineer jobs? Cities with the most Asic Dft Engineer job openings:
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Asic Dft Engineer jobs near you
Infographic showing various Asic Dft Engineer job openings in the United States as of May 2026, with employment types broken down into 17% Full Time, and 83% Contract. Highlights an 6% Physical, and 94% Remote job distribution, with an average salary of $158,244 per year, or $76.1 per hour.

Lead ASIC DFT engineer.

Accord Technologies Inc.

San Jose, CA • On-site

$194.60K/yr

Contractor

Posted 5 days ago

Job description

Role: Lead ASIC DFT Engineer
Location: San Jose, CA 
Work Setup: Remote however once/month in office. PST time zone preferred
Designation: Associate
Experience Required:
  • 10+ years of hands-on experience in ASIC Design-for-Test (DFT)
Role Summary:
We are seeking a highly experienced Lead ASIC DFT Engineer to architect, implement, verify, and debug advanced DFT solutions for complex ASIC and SoC designs. This role requires deep technical ownership across DFT architecture, scan insertion, ATPG, MBIST/LBIST, JTAG, boundary scan, and post-silicon validation, along with the ability to lead cross-functional debug efforts and drive resolution of critical silicon issues.
 
Key Skills Required:
  • Strong hands-on ASIC DFT experience with end-to-end ownership
  • Deep expertise in scan architecture, ATPG, MBIST, LBIST, JTAG, boundary scan, and silicon debug
  • Experience with Synopsys, Cadence, and Siemens/Mentor EDA tools
  • Strong background in scan insertion, scan chain stitching, ATPG setup, simulation, debug, and DRC analysis
  • MBIST implementation and verification; SMS experience preferred
  • Tessent/SSN experience preferred
  • Strong understanding of PLLs, RTL design, synthesis, LEC, and physical design flows
  • Post-silicon debug and silicon bring-up experience
  • TCL, PERL, or Python scripting experience is highly preferred