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Asic Dft Engineer Jobs (NOW HIRING)

Select Minds LLC

DFT Engineer

Lansing, MI · On-site

$65 - $130/hr

Opportunity for advancement DFT Engineer (Design for Test) Location: Santa Clara, CA (Onsite ... Design and implement DFT architecture for ASIC and SoC designs. * Develop and integrate Scan ...

Lorven Technologies

DFT Engineer

Santa Clara, CA · On-site

DFT Engineer Location: Santa Clara, CA Required Skills & Qualifications • 5+ years of hands-on experience in DFT and ATPG for SoC or ASIC designs • Strong understanding of DFT fundamentals ...

Qualcomm

DFT Engineer

San Diego, CA · On-site

$140K - $210K/yr

Engineering Group, Engineering Group > ASICS Engineering General Summary: As a leading technology ... The Digital ASIC Design Team is currently seeking candidates who will be responsible for the ...

Intel

DFT Application Engineer

Hillsboro, OR

Drive quality improvements in ASIC DFT/DFM and ATPG validation methodology, capability/flow, and ... Bachelor's degree in Electrical Engineering, Computer Engineering, or STEM-related field * 3+ years ...

Cisco

ASIC DFT STA Engineer

Santa Clara, CA

$165K - $241K/yr

Your Impact You will be in the Silicon One development organization as an ASIC DFT STA Engineer. You are a detail-oriented STA Engineer with strong analytical skills and a deep understanding of ...

Intel

DFT Application Engineer

Santa Clara, CA

Drive quality improvements in ASIC DFT/DFM and ATPG validation methodology, capability/flow, and ... Bachelor's degree in Electrical Engineering, Computer Engineering, or STEM-related field * 3+ years ...

Intel

DFT Application Engineer

Phoenix, AZ

Drive quality improvements in ASIC DFT/DFM and ATPG validation methodology, capability/flow, and ... Bachelor's degree in Electrical Engineering, Computer Engineering, or STEM-related field * 3+ years ...

Intel Corporation

DFT Application Engineer

Phoenix, AZ · On-site

Drive quality improvements in ASIC DFT/DFM and ATPG validation methodology, capability/flow, and ... Bachelor's degree in Electrical Engineering, Computer Engineering, or STEM-related field * 3+ years ...

Cisco

ASIC DFT STA Engineer

San Jose, CA · On-site

$165K - $241K/yr

Your Impact You will be in the Silicon One development organization as an ASIC DFT STA Engineer. You are a detail-oriented STA Engineer with strong analytical skills and a deep understanding of ...

Cirrus Logic

DFT Engineer (CE-64000920)

Chandler, AZ · On-site

For over four decades, Cirrus Logic has been propelled by the top engineers in mixed-signal ... Possess strong hands on working knowledge on ASIC DFT design and verification. * Experience in ...

Cisco

ASIC DFT STA Engineer

San Jose, CA

$165K - $241K/yr

Your Impact You will be in the Silicon One development organization as an ASIC DFT STA Engineer. You are a detail-oriented STA Engineer with strong analytical skills and a deep understanding of ...

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All JobsAsic Dft Engineer Jobs

Asic Dft Engineer information

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$82.5K

$158.2K

$167.5K

How much do asic dft engineer jobs pay per year?

As of Jul 18, 2026, the average yearly pay for asic dft engineer in the United States is $158,244.00, according to ZipRecruiter salary data. Most workers in this role earn between $166,000.00 and $166,000.00 per year, depending on experience, location, and employer.

What is the difference between Asic Dft Engineer vs Asic Verification Engineer?

AspectAsic Dft EngineerAsic Verification Engineer
Primary FocusDesign for Testability (DFT) implementation and validationFunctional verification of ASIC designs
Skills & CertificationsRTL design, DFT tools, scripting languagesHardware description languages, verification methodologies
Work EnvironmentDesign teams, DFT tool suitesVerification environments, simulation tools
Industry UsageSemiconductor, electronics manufacturingSemiconductor, electronics design companies

While both roles are integral to ASIC development, Asic Dft Engineers focus on ensuring designs are testable and manufacturable, whereas Asic Verification Engineers concentrate on verifying the correctness of the design before fabrication.

More about Asic Dft Engineer jobs
What cities are hiring for Asic Dft Engineer jobs? Cities with the most Asic Dft Engineer job openings:
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What job categories do people searching Asic Dft Engineer jobs look for? The top searched job categories for Asic Dft Engineer jobs are:
Asic Dft Engineer jobs near you
Infographic showing various Asic Dft Engineer job openings in the United States as of July 2026, with employment types broken down into 97% Full Time, 1% Part Time, and 2% Contract. Highlights an 89% Physical, 6% Hybrid, and 5% Remote job distribution, with an average salary of $158,244 per year, or $76.1 per hour.
DFT Engineer

DFT Engineer

Select Minds LLC

Lansing, MI • On-site

$65 - $130/hr

Full-time

Posted 11 days ago

Job description

Benefits:
  • Day-1 Onsite
  • Competitive salary
  • Opportunity for advancement

DFT Engineer (Design for Test)
Location: Santa Clara, CA (Onsite)
Employment Type: Long-Term Contract
Interview Process: Virtual Interviews
Compensation: Based on Experience (DOE)
Engagement: ANY
Preference: Local candidates or those able to work onsite
We are seeking an experienced DFT Engineer to join a high-performing ASIC/SoC engineering team.
In this role, you will be responsible for designing and implementing Design-for-Test (DFT) solutions that ensure high manufacturing quality, test coverage, and efficient production testing for complex semiconductor devices.
Key Responsibilities
  • Design and implement DFT architecture for ASIC and SoC designs.
  • Develop and integrate Scan Compression, MBIST, LBIST, JTAG, and IJTAG solutions.
  • Perform ATPG, fault simulation, and test coverage analysis.
  • Support silicon bring-up, debug, characterization, and production test activities.
  • Collaborate closely with Design, Verification, Physical Design, and Product Engineering teams throughout the development lifecycle.

Required Qualifications
5+ years of hands-on experience in Design for Test (DFT).
  • Strong expertise in Scan, Scan Compression, MBIST, LBIST, ATPG, and JTAG technologies.
  • Solid understanding of IEEE 1149.1, IEEE 1500, and IEEE 1687 (IJTAG) standards.
  • Experience with one or more industry-standard DFT tools:
    • Synopsys TestMAX / DFT Compiler
    • Siemens Tessent
    • Cadence Modus
  • Proficiency in Verilog and/or SystemVerilog.
  • Scripting experience using Python, Perl, Tcl, or Shell.
  • Preferred Qualifications
  • Experience with ASIC/SoC development.
  • Background in silicon bring-up, debug, and production test.
  • Strong problem-solving skills and the ability to work effectively in cross-functional engineering teams.

If you're passionate about developing robust DFT solutions for advanced semiconductor products, we'd love to hear from you.
Compensation: $65.00 - $130.00 per hour
About Us
We work to deliver profitability in your business - with effective communication, consulting, and interactive solutions. Following an Agile Work Approach, we make sure you get the ideal solutions at minimum expenses.
Work Approach
Our Philosophy
Our Philosophy starts-and-ends at the Client-first approach. Be it understanding your business requirements to choosing the right technologies, we work as a collective team that takes all the possible steps to grow continuously towards our common goal.
Work Policy
We promote a collaborative work environment. We involve everyone working in the organization in community decisions and encourage them to think from a broader perspective. Our work process promotes flexibility and we maintain a high level of discipline at different levels of execution.
The Future
SelectMinds have years of experience in the domain helps us understand the need-of-the-hour better. This understanding drives us to a better future with every minute ticking. We believe we will be taking off major businesses from their flagship positions, with the products we are eyeing today.

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