ZipRecruiter

Log In

1

Asic Engineering Jobs (NOW HIRING)

Cisco

ASIC Engineering Program Manager

San Jose, CA · On-site

$210K - $305K/yr

Lead multi-functional infrastructure and ASIC development projects from concept through production, coordinating efforts across Silicon Engineering, Platform, Software, Hardware Systems, Sourcing ...

Cisco

ASIC Engineering Program Manager

San Jose, CA · On-site

$210K - $305K/yr

Lead multi-functional infrastructure and ASIC development projects from concept through production, coordinating efforts across Silicon Engineering, Platform, Software, Hardware Systems, Sourcing ...

Trinity Technology Solutions

ASIC Engineer

San Jose, CA · On-site

$194K/yr

Senior ASIC ENGINEER Location : San Jose,CA - Onsite Duration : Permanent Direct Hire About the job: Senior ASIC Engineer San Jose, CA-onsite $230k Our client, a cutting-edge developer of custom ...

Jobsbridge

ASIC Engineer

San Jose, CA · On-site

$194K/yr

ASIC Engineer Location: San Jose, CA Duration: 6 Months Minimum Required Skills: ASIC Design, FPGA, RTL Design, Chip Architecture, ASIC, Implementation,Synthesis /Conformal (Cadence Tool for formal ...

Cisco

ASIC Engineering Technical Leader- STA

San Jose, CA · On-site

$210K - $305K/yr

Define, design and verify ASIC and ASIC subsystems to be deployed in a range of Cisco platforms. Contribute to a multi-disciplined engineering team to meet the power, performance, and area goals for ...

next page

Showing results 1-20

All JobsAsic Engineering Jobs

Asic Engineering information

See salary details

$82.5K

$158.2K

$167.5K

How much do asic engineering jobs pay per year?

As of Jul 29, 2026, the average yearly pay for asic engineering in the United States is $158,244.00, according to ZipRecruiter salary data. Most workers in this role earn between $166,000.00 and $166,000.00 per year, depending on experience, location, and employer.

How much does an ASIC engineer make?

ASIC engineers typically earn a median salary ranging from $100,000 to $150,000 annually, depending on experience, location, and industry. Entry-level positions may start around $80,000, while senior roles with specialized skills in hardware description languages and verification tools can exceed $180,000. Compensation often includes benefits such as bonuses and stock options in technology companies.

What engineer makes $500,000 a year?

In the field of ASIC engineering, senior-level engineers with extensive experience, specialized skills in chip design, and leadership roles can earn salaries approaching or exceeding $500,000 annually, especially in high-cost-of-living areas or within large technology companies. Such compensation often includes bonuses, stock options, and other incentives. Achieving this level typically requires advanced degrees, certifications, and a proven track record of successful projects.

Are ASIC engineers in demand?

ASIC engineers are in high demand due to the growing need for custom integrated circuits in industries like telecommunications, consumer electronics, and automotive. Skills in hardware description languages such as VHDL or Verilog, along with experience in chip design and verification, enhance job prospects in this field.

What does a ASIC engineer do?

An ASIC engineer designs, develops, and tests application-specific integrated circuits used in electronic devices. They work with hardware description languages like VHDL or Verilog, collaborate with cross-functional teams, and ensure the circuits meet performance and power requirements. Proficiency in digital design, simulation tools, and understanding of manufacturing processes are essential for this role.

What is the difference between Asic Engineering vs FPGA Design?

AspectAsic EngineeringFPGA Design
Required CredentialsBachelor's or Master's in Electrical Engineering, VLSI, or related fields; often certifications in ASIC designBachelor's or Master's in Electrical Engineering, Digital Design, or related fields; certifications less common
Work EnvironmentDesigning custom chips in semiconductor labs or design houses; involves hardware and software integrationDeveloping programmable logic designs in labs or FPGA development environments; focuses on reconfigurable hardware
Industry UsageUsed in high-volume consumer electronics, telecom, and automotive industries for custom chip solutionsCommon in prototyping, testing, and specialized applications across various industries

Asic Engineering and FPGA Design share foundational knowledge in digital logic and hardware description languages. However, Asic Engineers focus on designing permanent, high-volume chips, while FPGA Designers work with reconfigurable hardware for testing and specialized tasks. Both roles require similar educational backgrounds but differ in application and design processes.

More about Asic Engineering jobs
What cities are hiring for Asic Engineering jobs? Cities with the most Asic Engineering job openings:
What states have the most Asic Engineering jobs? States with the most job openings for Asic Engineering jobs include:
What job categories do people searching Asic Engineering jobs look for? The top searched job categories for Asic Engineering jobs are:
Asic Engineering jobs near you
Infographic showing various Asic Engineering job openings in the United States as of July 2026, with employment types broken down into 17% As Needed, 80% Full Time, 2% Contract, and 1% Summer. Highlights an 85% Physical, 9% Hybrid, and 6% Remote job distribution, with an average salary of $158,244 per year, or $76.1 per hour.

Sr. ASIC EDA Workflow Engineer

Tensordyne

Sunnyvale, CA • On-site

Full-time

Posted 5 days ago

Job description

Job Summary:
Tensordyne is an AI system solution company that builds high-performance generative AI inference systems. The Sr. ASIC EDA Workflow Engineer will lead EDA tool flow management and engineering workflow development, optimizing and improving EDA workflows for ASIC design processes in a fast-paced, agile environment.
Responsibilities:
• Lead EDA tool flow management, and associated engineering workflow development for multimodal generative AI inference acceleration products.
• Guide and assist colleagues to improve and invent EDA workflows within a fast-paced, agile HPC development environment.
• Drive optimization, implementation and exploration of new EDA tools and technologies for the full ASIC chip design process.
• Continuously innovate and improve scalable, reliable, high-performance systems and tools to enable the next generation of products.
• Work closely with ASIC team members engaged in the design and verification of products to understand and improve their workflows and EDA needs.
Qualifications:
Required:
• Experience leading the development and support for compilation, build automation, testing, packaging and installation project generators that build object files like either CMake, GNU make, and/or Ninja, as well as experience with CI/CD and modern Git Branching workflows.
• Hands-on ASIC engineering experience, that includes knowledge of VLSI/SoC chip design and verification workflows, with ASIC EDA tool suites from Synopsys and/or Cadence.
• Knowledge of Linux system administration and familiarity with cloud-based devops, with experience in supporting EDA tools.
• Programming and debugging skills with key languages to automate tasks and improve efficiency using scripts.
• Prior work experience with supporting ASIC engineers with EDA workflows, including installation of new tool versions, FlexLM license management, and debugging/fixing issues with EDA vendors.
• Excellent analytical, written, and verbal interpersonal skills along with an ability to productively collaborate within a global engineering team that moves at a startup pace.
• Bachelor’s or Master's degree in Computer Science, Computer Engineering, Electrical Engineering or a related technical field.
Company:
Tensordyne is a technology company involved in building AI math, chips, hardware, and software in order to make AI affordable and efficient. Founded in 2017, the company is headquartered in Sunnyvale, USA, with a team of 51-200 employees. The company is currently Growth Stage.

Apply