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Google Asic Design Engineer Jobs (NOW HIRING)

Fusion408

Principal ASIC Design Engineer

Carlsbad, CA · On-site

Principal ASIC Design Engineer Description: Expertise in at least 3 of the following: communication system design, RF radio design, digital ASIC design, applications platforms, and semiconductor ...

Atom Computing

Principal ASIC Design Engineer

Boulder, CO

$180K - $220K/yr

... engineering, specifically in ASIC/SoC environments. Qualifications * Have gone through 2 or more complete ASIC design cycles. * Experience porting designs from FPGA prototypes to ASICs * Proficiency ...

ServerLogic

Senior ASIC Design Engineer

Beaverton, OR · On-site

Sr/ ASIC Design Engineer (5+ Years of Experience) DESCRIPTION OF POSITION/DUTIES - * Architect a block of an ASIC and write a microarchitecture specification (MAS) for the block * Collaborate with ...

Atom Computing

Principal ASIC Design Engineer

Austin, TX · On-site

$180K - $220K/yr

... engineering, specifically in ASIC/SoC environments. Qualifications * Have gone through 2 or more complete ASIC design cycles. * Experience porting designs from FPGA prototypes to ASICs * Proficiency ...

Credo, Inc

Principal ASIC Design Engineer

San Jose, CA · On-site

$180K - $210K/yr

About the Role As a Principal ASIC Design Engineer, you will be responsible for all aspects of front-end ASIC design, including RTL implementation and verification of complex logic blocks. You will ...

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Google Asic Design Engineer information

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$94K

$150.2K

$202K

How much do google asic design engineer jobs pay per year?

As of Jun 16, 2026, the average yearly pay for google asic design engineer in the United States is $150,195.00, according to ZipRecruiter salary data. Most workers in this role earn between $131,500.00 and $180,000.00 per year, depending on experience, location, and employer.

What is the difference between Google Asic Design Engineer vs Google FPGA Design Engineer?

AspectGoogle Asic Design EngineerGoogle FPGA Design Engineer
Required CredentialsBachelor's/Master's in Electrical Engineering or Computer Engineering; experience in ASIC designBachelor's/Master's in Electrical Engineering or Computer Engineering; FPGA design experience
Work EnvironmentDesigning custom silicon chips for Google productsDeveloping and testing FPGA prototypes for hardware acceleration
Employer & Industry UsagePrimarily in semiconductor and hardware design teams at GoogleHardware prototyping and acceleration teams at Google

The main difference between a Google Asic Design Engineer and a Google FPGA Design Engineer lies in their focus: ASIC engineers design custom chips for optimized performance, while FPGA engineers develop flexible hardware prototypes using field-programmable gate arrays. Both roles require strong electrical engineering skills but serve different stages of hardware development.

How does a Google ASIC Design Engineer typically collaborate with cross-functional teams during the chip development process?

As a Google ASIC Design Engineer, you will work closely with teams such as architecture, verification, software, and hardware validation to ensure successful chip delivery. Collaboration often involves regular meetings to align on design specifications, resolve integration issues, and discuss performance optimization. Effective communication is essential, as you’ll need to translate requirements from system architects into detailed hardware designs and provide feedback to verification and validation teams. This cross-functional interaction fosters a dynamic work environment and helps ensure the final product meets Google's rigorous standards.

What does a Google ASIC Design Engineer do?

A Google ASIC Design Engineer is responsible for designing and developing custom integrated circuits, known as Application-Specific Integrated Circuits (ASICs), that power Google's data centers, cloud infrastructure, and consumer devices. Their work involves collaborating with cross-functional teams to define requirements, create architecture, perform logic and physical design, and validate the silicon before production. They use advanced design tools and methodologies to ensure high performance, low power consumption, and reliability. Ultimately, their contributions help improve the efficiency and capabilities of Google's hardware products.

What are the key skills and qualifications needed to thrive as a Google ASIC Design Engineer, and why are they important?

To thrive as a Google ASIC Design Engineer, you need a strong background in electrical engineering, digital logic design, and experience with ASIC development, typically backed by a relevant degree. Familiarity with hardware description languages (such as Verilog or VHDL), EDA tools (like Synopsys or Cadence), and an understanding of SoC architectures are essential, and related certifications can be valuable. Strong problem-solving skills, attention to detail, and effective teamwork and communication abilities help set candidates apart. These skills are crucial for designing reliable, high-performance ASICs that meet Google's specifications and project timelines.
More about Google Asic Design Engineer jobs
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Google Asic Design Engineer jobs near you
Infographic showing various Google Asic Design Engineer job openings in the United States as of June 2026, with employment types broken down into 84% Full Time, 8% Part Time, and 8% Contract. Highlights an 41% In-person, 17% Hybrid, and 42% Remote job distribution, with an average salary of $150,195 per year, or $72.2 per hour.

ASIC Design Engineer - Remote

Futran Tech Solutions Pvt. Ltd.

Remote

Full-time

Posted 3 days ago

Job description

ASIC Design Engineer(Remote)
MUST HAVE: AEROSPACE , DEEP UNDERSTANDING ASIC, DO254, DIGITAL CIRCUITS
Position Overview:
We are looking for an experienced ASIC Design Engineer with a strong background in the design, verification, and implementation of Application-Specific Integrated Circuits (ASICs) for aerospace applications. The ideal candidate will have extensive experience working on high-reliability, high-performance digital circuits, and a deep understanding of ASIC design processes, in consideration of DO254.
  1. Key Responsibilities:
  • ASIC Design and Development: Design and develop high-performance, low-power, and highly reliable ASICs for aerospace systems, ensuring compliance with stringent aerospace industry standards like DO254 .
  • System-Level Design Integration: Work closely with system engineers to ensure seamless integration of ASICs into larger aerospace systems, including payloads, communications, and avionics systems.
  • Verification and Testing: Conduct thorough verification and validation of ASIC designs, including functional verification, timing analysis, and design for testability (DFT). Perform failure analysis and debug of complex ASIC designs.
  • RTL Design & Simulation: Write RTL (Register Transfer Level) code in Verilog or VHDL, and perform simulations using industry-standard tools like ModelSim, Cadence, or Synopsys.
  • Design for Reliability: Focus on designing for high-reliability and radiation tolerance,
  • Cross-Functional Collaboration: Collaborate with cross-functional teams like = hardware engineers, software engineers, and test engineers.
  1. Qualifications & Skills:
  • Education: Bachelor's, Master's, or PhD degree in Electrical Engineering, Computer Engineering, or a related field.
  • Experience:
    • Minimum of 5-8 years of hands-on experience in ASIC design for aerospace, defense.
    • Proven expertise in designing ASICs that meet high-reliability standards, such as MIL-STD-883, DO-254, or other aerospace-specific certifications.
    • Solid understanding of digital design, RTL coding (Verilog/VHDL), and ASIC flow (synthesis, place & route, timing analysis).
    • Experience with ASIC verification techniques (e.g., functional verification, simulation, emulation, DFT).
    • Knowledge of radiation-hardened (Rad-Hard) or radiation-tolerant ASIC design principles is a plus.
  • Technical Skills:
    • Expertise in Verilog/ VHDL and experience with ASIC synthesis tools like Cadence Genus, Synopsys Design Compiler.
    • Experience with simulation tools such as ModelSim, VCS, or Xilinx Vivado.
    • Familiarity with timing analysis, power optimization, and signal integrity.
    • Experience in FPGA/ASIC hybrid systems and custom digital logic development.
    • Knowledge of PCB design principles and experience working with high-speed boards is a plus.
  • Soft Skills:
    • Excellent problem-solving and analytical skills, with the ability to troubleshoot complex system-level issues.
    • Strong communication skills to interact with cross-functional teams, including engineers, management, and customers.
    • Ability to work independently with minimal supervision, while also collaborating in a team-oriented environment.
    • Detail-oriented and committed to maintaining high standards of quality, safety, and reliability.
  1. Preferred Previous Experience:
  • Experience with space-based electronics or aerospace communications.
  • Familiarity with ISO 9001, AS9100, or similar quality standards in aerospace.
  • Background in radiation effects on electronics or space environmental testing.
  • Familiarity with FPGA-based ASIC prototyping for aerospace applications.

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