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Google Asic Design Engineer Jobs in Arizona (NOW HIRING)

Prattwhitney

Senior FPGA Design Engineer

Tucson, AZ · On-site

$86.80 - $165.20/hr

  • Medical

  • Dental

  • Vision

  • Life

  • Retirement

  • PTO

Lead small teams and mentor junior engineers. * Support internal and external technical reviews ... Experience with FPGA/ASIC design, including VHDL and/or Verilog coding or FPGA/ASIC verification ...

NXP Semiconductors

Principal Engineer

Chandler, AZ · On-site

$174K/yr

Duties: Perform semiconductor engineering design, development, and testing for firm products and ... ASIC design verification; 8. Regression management and artifact tracking; 9. C-based test ...

NXP Semiconductors N.V.

Principal Engineer

Chandler, AZ · On-site

$174K/yr

Duties: Perform semiconductor engineering design, development, and testing for firm products and ... ASIC design verification; 8. Regression management and artifact tracking; 9. C-based test ...

NXP Semiconductors N.V.

Principal Engineer

Chandler, AZ · On-site

$174K/yr

Duties: Perform semiconductor engineering design, development, and testing for firm products and ... ASIC design verification; 8. Regression management and artifact tracking; 9. C-based test ...

Intelliswift Software

Physical Design Engineer

Phoenix, AZ · On-site

$135K - $139K/yr

... ASIC/SoC design Min. * Qualifications: 0-1 yrs of exp. Enginner - CL11 & CL10 Master's degree in Electrical Eng. or Comp. Science RTL2GDSII exp. on advanced tech. nodes (7nm and below) Exp. w/low ...

Cirrus Logic

Digital Design Engineer

Chandler, AZ · On-site

$133K/yr

For over four decades, Cirrus Logic has been propelled by the top engineers in mixed-signal ... Exposure to low-power and high-performance ASIC design techniques. * Experience with back-end flows ...

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Google Asic Design Engineer information

See Arizona salary details

$87.6K

$140K

$188.2K

How much do google asic design engineer jobs pay per year?

As of Aug 16, 2026, the average yearly pay for google asic design engineer in Arizona is $139,965.00, according to ZipRecruiter salary data. Most workers in this role earn between $122,500.00 and $167,700.00 per year, depending on experience, location, and employer.

What is the difference between Google Asic Design Engineer vs Google FPGA Design Engineer?

AspectGoogle Asic Design EngineerGoogle FPGA Design Engineer
Required CredentialsBachelor's/Master's in Electrical Engineering or Computer Engineering; experience in ASIC designBachelor's/Master's in Electrical Engineering or Computer Engineering; FPGA design experience
Work EnvironmentDesigning custom silicon chips for Google productsDeveloping and testing FPGA prototypes for hardware acceleration
Employer & Industry UsagePrimarily in semiconductor and hardware design teams at GoogleHardware prototyping and acceleration teams at Google

The main difference between a Google Asic Design Engineer and a Google FPGA Design Engineer lies in their focus: ASIC engineers design custom chips for optimized performance, while FPGA engineers develop flexible hardware prototypes using field-programmable gate arrays. Both roles require strong electrical engineering skills but serve different stages of hardware development.

How does a Google ASIC Design Engineer typically collaborate with cross-functional teams during the chip development process?

As a Google ASIC Design Engineer, you will work closely with teams such as architecture, verification, software, and hardware validation to ensure successful chip delivery. Collaboration often involves regular meetings to align on design specifications, resolve integration issues, and discuss performance optimization. Effective communication is essential, as you’ll need to translate requirements from system architects into detailed hardware designs and provide feedback to verification and validation teams. This cross-functional interaction fosters a dynamic work environment and helps ensure the final product meets Google's rigorous standards.

What does a Google ASIC Design Engineer do?

A Google ASIC Design Engineer is responsible for designing and developing custom integrated circuits, known as Application-Specific Integrated Circuits (ASICs), that power Google's data centers, cloud infrastructure, and consumer devices. Their work involves collaborating with cross-functional teams to define requirements, create architecture, perform logic and physical design, and validate the silicon before production. They use advanced design tools and methodologies to ensure high performance, low power consumption, and reliability. Ultimately, their contributions help improve the efficiency and capabilities of Google's hardware products.

What are the key skills and qualifications needed to thrive as a Google ASIC Design Engineer, and why are they important?

To thrive as a Google ASIC Design Engineer, you need a strong background in electrical engineering, digital logic design, and experience with ASIC development, typically backed by a relevant degree. Familiarity with hardware description languages (such as Verilog or VHDL), EDA tools (like Synopsys or Cadence), and an understanding of SoC architectures are essential, and related certifications can be valuable. Strong problem-solving skills, attention to detail, and effective teamwork and communication abilities help set candidates apart. These skills are crucial for designing reliable, high-performance ASICs that meet Google's specifications and project timelines.

What are popular job titles related to Google Asic Design Engineer jobs in Arizona?

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What job categories do people searching Google Asic Design Engineer jobs in Arizona look for?

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What cities in Arizona are hiring for Google Asic Design Engineer jobs?

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Google Asic Design Engineer jobs near you
Infographic showing various Google Asic Design Engineer job openings in Arizona as of August 2026, with employment types broken down into 6% As Needed, 72% Full Time, and 22% Contract. Highlights an 94% In-person, and 6% Remote job distribution, with an average salary of $139,965 per year, or $67.3 per hour.

Senior Applications and Solutions Engineer - Foundry Services

Intel Corporation

Phoenix, AZ • On-site

$122.44 - $232.19/hr

Other

Re-posted 11 days ago

Intel rating

8.7

Company rating: 8.7 out of 10

Based on 147 frontline employees who took The Breakroom Quiz

19th of 157 rated electronics manufacturers

Job description

Position Overview

We seek a Senior ASIC Design Engineer who will provide technical support to Intel Foundry Services customers on PDKs through ASIC design implementation flows and perform ASIC physical design execution focused on complex multi-voltage domain (UPF/CPF) designs and power-intent (VCLP and Conformal LP) verification signoff. This role drives quality improvements in design kits, supports customers through successful tape-outs, and performs ASIC design services on complex multi-voltage domain designs.

Key Responsibilities
  • Provide comprehensive technical support to Intel Foundry Services customers on PDKs, digital reference flows, and digital design signoff methodologies in multi-voltage domain implementation and verification.
  • Support and deliver ASIC/Digital tool/flow/methodology solutions, especially in multi-voltage domain design implementation and verification using Cadence and Synopsys tool suites.
  • Have deep knowledge of UPF/CPF (level-shifter, isolation, power gating, retention, always-on) implementation and verification using VCLP and Conformal LP; write and debug UPF/CPF for multi-voltage domain designs.
  • Drive customer success through expert guidance and hands-on experience in ASIC design execution.
  • Drive quality improvements in design kits and documentation through ASIC design reference flow validation and comprehensive documentation review.
  • Create application notes, technical design checklists, and deliver training presentations to customers and internal teams.
  • Establish and maintain high-quality design through implementation and verification methodologies and checklists.
Core Competencies
  • Self-driven and results-oriented with ability to manage multiple tasks effectively.
  • Strong teamwork skills to drive solutions for implementation challenges.
  • Excellent analytical problem-solving capabilities for complex design issues.
  • Effective communication skills with experience in collaboration and customer feedback.
Minimum Qualifications
  • US citizenship required.
  • Ability to obtain a US Government Security Clearance.
  • Bachelor’s degree in Electrical / Computer Engineering, Computer Science, or a STEM related field.
  • 4+ years of experience with advanced CMOS processes (16 nm and below).
  • 3+ years of experience in ASIC design implementation and verification in low power, multi-voltage domain.
  • 3+ years of experience in scripting languages such as Python, Perl, Tcl, and/or shell scripting.
Preferred Qualifications
  • Active US Government Security Clearance with at least Secret level.
  • Post-graduate degree in Electrical / Computer Engineering, Computer Science, or a STEM related field.
  • Experience with state-of-the-art process technology (7 nm and below).
  • Hands-on experience in physical design implementation and verification methodology for multi-voltage domain in SoC design.
  • Experience using EDA tools for multi-power domain design (UPF/CPF) implementation and power-intent verification (VCLP, Conformal LP) at block and SOC level.
  • Experience in writing and debugging UPF/CPF for multi-voltage domain designs.
  • Customer-facing experience in technical support roles.
Benefits and Work Arrangement
  • Annual salary range: $122,440.00 – $232,190.00 USD (US locations).
  • Hybrid work model allowing split between on-site and off-site work.
EEO Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

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About Intel

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Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore's Law to bring smart, connected devices to every person on Earth

Industry

Manufacturing

Company size

10,000+ Employees

Headquarters location

Santa Clara, CA, US

Year founded

1968

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