RTL Design Engineer
Phoenix, AZ · On-site
... Engineering At least 1+ years of coursework or experience in each the following areas: o Basic Logic Design o Microprocessors o Computer Architecture o Digital design and RTL coding o Verilog ...
Phoenix, AZ · On-site
... Engineering At least 1+ years of coursework or experience in each the following areas: o Basic Logic Design o Microprocessors o Computer Architecture o Digital design and RTL coding o Verilog ...
Phoenix, AZ · On-site
... Engineering At least 1+ years of coursework or experience in each the following areas: o Basic Logic Design o Microprocessors o Computer Architecture o Digital design and RTL coding o Verilog ...
Phoenix, AZ · On-site
$141K - $269K/yr
As a CPU Logic Design Engineer, you will play a critical role in designing and optimizing the logic for Intel's cutting-edge processors. You will drive the development of register transfer level (RTL ...
Phoenix, AZ · On-site
$141K - $269K/yr
As a CPU Logic Design Engineer, you will play a critical role in designing and optimizing the logic for Intel's cutting-edge processors. You will drive the development of register transfer level (RTL ...
As a Senior CPU RTL Design Engineer, you will define, develop, and optimize key microarchitectural features that power Intel's next-generation processors. In this role, you will contribute to CPU ...
As a Senior CPU RTL Design Engineer, you will define, develop, and optimize key microarchitectural features that power Intel's next-generation processors. In this role, you will contribute to CPU ...
Phoenix, AZ · On-site
$164K - $269K/yr
As a Senior CPU RTL Design Engineer - Power Management , you will play a critical role in designing and delivering CPU microarchitectures with strong emphasis on power management and energy-efficient ...
Phoenix, AZ · On-site
$164K - $269K/yr
As a Senior CPU RTL Design Engineer - Power Management , you will play a critical role in designing and delivering CPU microarchitectures with strong emphasis on power management and energy-efficient ...
Chandler, AZ · On-site
$133K/yr
Develop RTL designs using Verilog and support integration into larger SoC environments. * Design ... Exposure to low-power and high-performance ASIC design techniques. * Experience with back-end flows ...
Chandler, AZ · On-site
$133K/yr
Develop RTL designs using Verilog and support integration into larger SoC environments. * Design ... Exposure to low-power and high-performance ASIC design techniques. * Experience with back-end flows ...
Chandler, AZ · On-site
$133K/yr
Develop RTL designs using Verilog and support integration into larger SoC environments. * Design ... Exposure to low-power and high-performance ASIC design techniques. * Experience with back-end flows ...
Chandler, AZ · On-site
$133K/yr
Develop RTL designs using Verilog and support integration into larger SoC environments. * Design ... Exposure to low-power and high-performance ASIC design techniques. * Experience with back-end flows ...
Chandler, AZ · On-site
$133K/yr
Develop RTL designs using Verilog and support integration into larger SoC environments. * Design ... Exposure to low-power and high-performance ASIC design techniques. * Experience with back-end flows ...
Chandler, AZ · On-site
$133K/yr
Develop RTL designs using Verilog and support integration into larger SoC environments. * Design ... Exposure to low-power and high-performance ASIC design techniques. * Experience with back-end flows ...
Chandler, AZ · On-site
$133K/yr
Develop RTL designs using Verilog and support integration into larger SoC environments. * Design ... Exposure to low-power and high-performance ASIC design techniques. * Experience with back-end flows ...
Chandler, AZ · On-site
$133K/yr
Develop RTL designs using Verilog and support integration into larger SoC environments. * Design ... Exposure to low-power and high-performance ASIC design techniques. * Experience with back-end flows ...
Chandler, AZ · On-site
$150 - $200/hr
Integrate RTL into larger subsystem and SoC environments * Support lint, CDC/RDC, synthesis, and design quality checks * Collaborate with physical design teams to resolve implementation issues ...
Chandler, AZ · On-site
$150 - $200/hr
Integrate RTL into larger subsystem and SoC environments * Support lint, CDC/RDC, synthesis, and design quality checks * Collaborate with physical design teams to resolve implementation issues ...
Chandler, AZ · On-site
$150K - $200K/yr
Integrate RTL into larger subsystem and SoC environments * Support lint, CDC/RDC, synthesis, and design quality checks * Collaborate with physical design teams to resolve implementation issues ...
Chandler, AZ · On-site
$150K - $200K/yr
Integrate RTL into larger subsystem and SoC environments * Support lint, CDC/RDC, synthesis, and design quality checks * Collaborate with physical design teams to resolve implementation issues ...
Chandler, AZ · On-site
We are seeking a Senior Engineer I - design to join our team. This role involves RTL design ... optimize RTL (Verilog/SystemVerilog) for digital blocks and subsystems targeting ASIC ...
Chandler, AZ · On-site
We are seeking a Senior Engineer I - design to join our team. This role involves RTL design ... optimize RTL (Verilog/SystemVerilog) for digital blocks and subsystems targeting ASIC ...
Chandler, AZ · On-site
We are seeking a Senior Engineer I - design to join our team. This role involves RTL design ... optimize RTL (Verilog/SystemVerilog) for digital blocks and subsystems targeting ASIC ...
Chandler, AZ · On-site
We are seeking a Senior Engineer I - design to join our team. This role involves RTL design ... optimize RTL (Verilog/SystemVerilog) for digital blocks and subsystems targeting ASIC ...
Chandler, AZ · On-site
This is a hands-on role spanning RTL design, integration, and signoff verification-with broad cross ... ASIC/SoC Digital Design and Verification * Strong foundations in digital logic / finite state ...
Chandler, AZ · On-site
This is a hands-on role spanning RTL design, integration, and signoff verification-with broad cross ... ASIC/SoC Digital Design and Verification * Strong foundations in digital logic / finite state ...
Chandler, AZ · On-site
This is a hands-on role spanning RTL design, integration, and signoff verification-with broad cross ... ASIC/SoC Digital Design and Verification * Strong foundations in digital logic / finite state ...
Chandler, AZ · On-site
This is a hands-on role spanning RTL design, integration, and signoff verification-with broad cross ... ASIC/SoC Digital Design and Verification * Strong foundations in digital logic / finite state ...
Work closely with Analog and Verification engineers to deliver high-quality silicon solutions ... Fluent in Verilog / SystemVerilog RTL for digital CMOS circuit design. Strong understanding of ASIC ...
Work closely with Analog and Verification engineers to deliver high-quality silicon solutions ... Fluent in Verilog / SystemVerilog RTL for digital CMOS circuit design. Strong understanding of ASIC ...
Chandler, AZ · On-site
$133K/yr
... Engineer to join our growing hardware development team in Chandler, AZ. In this role, you will be ... RTL for digital CMOS circuit design. • Strong understanding of ASIC design methodology. • ...
Chandler, AZ · On-site
$133K/yr
... Engineer to join our growing hardware development team in Chandler, AZ. In this role, you will be ... RTL for digital CMOS circuit design. • Strong understanding of ASIC design methodology. • ...
... RTL for digital CMOS circuit design. · Strong understanding of ASIC design methodology. · Strong understanding of Lint, CDC & RDC tools. · Strong understanding of block-level & chip-level ...
Quick apply
... RTL for digital CMOS circuit design. · Strong understanding of ASIC design methodology. · Strong understanding of Lint, CDC & RDC tools. · Strong understanding of block-level & chip-level ...
Scottsdale, AZ · On-site
$122K - $136K/yr
... ASIC (Application Specific Integrated Circuit) and/or FPGA (Field Programmable Gate Array ... RTL coding and be proficient in micro-architecture design. Successful candidates will have an ...
Scottsdale, AZ · On-site
$122K - $136K/yr
... ASIC (Application Specific Integrated Circuit) and/or FPGA (Field Programmable Gate Array ... RTL coding and be proficient in micro-architecture design. Successful candidates will have an ...
Scottsdale, AZ · On-site
$119K - $164K/yr
... ASIC (Application Specific Integrated Circuit) and/or FPGA (Field Programmable Gate Array ... RTL coding and be proficient in micro-architecture design. Successful candidates will have an ...
Scottsdale, AZ · On-site
$119K - $164K/yr
... ASIC (Application Specific Integrated Circuit) and/or FPGA (Field Programmable Gate Array ... RTL coding and be proficient in micro-architecture design. Successful candidates will have an ...
Proficient in RTL design (Verilog/System Verilog), Low-power design, synthesis, timing constraint ... Experience with ASIC design flow including LINT, Formal, CDC/RDC, power estimations, MBIST/DFT ...
Proficient in RTL design (Verilog/System Verilog), Low-power design, synthesis, timing constraint ... Experience with ASIC design flow including LINT, Formal, CDC/RDC, power estimations, MBIST/DFT ...
| Aspect | Locum Asic Rtl Design Engineer | Contract Asic Rtl Design Engineer |
|---|---|---|
| Credentials | Typically requires relevant engineering degrees and RTL design experience | Similar credentials, often with specific RTL design certifications |
| Work Environment | Temporary, short-term assignments often in multiple locations | Project-based roles, usually in a fixed location or remote |
| Employer Usage | Used by agencies or companies needing immediate, short-term expertise | Engaged by companies or staffing agencies for project-specific work |
Both roles involve RTL design skills for ASIC development, but a Locum Asic Rtl Design Engineer typically fills short-term, temporary positions, often through staffing agencies, while a Contract Asic Rtl Design Engineer is engaged for specific projects with defined durations. The main difference lies in the nature and duration of employment, but both require similar technical credentials and work environments.
The most popular types of Asic Rtl Design Engineer jobs in Arizona are:
For Locum Asic Rtl Design Engineer jobs in Arizona, the most frequently searched job titles are:
The top searched job categories for Locum Asic Rtl Design Engineer jobs in Arizona are:
Cities in Arizona with the most Locum Asic Rtl Design Engineer job openings:

Develop logic design and RTL coding for CPU components such as cell libraries, functional units, and CPU IP blocks.
Participate in defining architecture and microarchitecture features to optimize CPU performance, power, and area.
Review and refine verification plans and tests to ensure correct implementation of design features.
8.7
Based on 147 frontline employees who took The Breakroom Quiz
18th of 161 rated electronics manufacturers
Intel is shaping the future of technology to help create a better future for the entire world. Our work in pushing forward fields like AI, analytics, and cloud-to-edge technology is at the heart of countless innovations. With a career at Intel, you'll have the opportunity to use technology to power major breakthroughs and create enhancements that improve our everyday quality of life. Join us and help make the future more wonderful for everyone. Want to learn more? Visit our YouTube Channel or the link below.
Life at Intel
As a CPU Logic Design Engineer, you will play a critical role in shaping Intel's next-generation, high-performance microprocessors. Leveraging your technical expertise, you will contribute to the design, development, and optimization of CPUs that drive innovative computing solutions across various industries. By developing cutting-edge logic designs and collaborating with a dynamic, cross-functional team, you will help Intel deliver world-class processors that meet the demands of modern computing applications, including energy-efficient performance and advanced functionality. Your work will directly impact Intel's mission to create world-changing technology and enrich the lives of every person on earth.
Key Responsibilities:
- Develop logic design and register transfer level (RTL) coding for CPU components, such as cell libraries, functional units, and CPU IP blocks.
- Participate actively in defining architecture and microarchitecture features to optimize CPU performance, power, and area.
- Write RTL and employ strategies to meet power, performance, area, and timing goals while ensuring design integrity and readiness for physical implementation.
- Review and refine verification plans and tests to ensure correct implementation of design features.
- Resolve failing RTL tests and implement corrective measures to meet design specifications.
- Document microarchitectural specifications (MAS) for CPU features and ensure their alignment with project goals.
- Support SoC customers to achieve seamless integration of the CPU block into larger designs.
A highly qualified candidate will exhibit the following behavior traits:
Demonstrated written and oral communication skills, particularly to an executive audience
Skilled at presenting complex information in a simple form.
Willingness to thrive in high stress, ambiguous environments, to climb very steep learning curves and rapidly distinguish what is important from what is not important.
Qualifications:Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
Minimum Qualifications
The candidate must have a Bachelor's Degree in Electrical or Computer Engineering or any STEM related education with at least 2+ years of experience -OR- Master's Degree in Electrical or Computer Engineering
At least 1+ years of coursework or experience in each the following areas:
o Basic Logic Design
o Microprocessors
o Computer Architecture
o Digital design and RTL coding
o Verilog/SystemVerilog and/or VHDL
o Synthesis tools (Design Compiler, Genus)
o Scripting languages (Python, Perl, TCL)
Preferred Qualifications
- Knowledge of energy-efficient and low-power logic design techniques, including optimization for high-frequency applications.
- Familiarity with software tools and methodologies used in RTL design, verification, and simulation.
- Understanding of Intel Architecture ISA and system architecture, including x86 assembly language.
- Experience in high-speed circuit design and optimization for datapath circuits and arrays.
- Knowledge of circuit planning, timing convergence, and other advanced design techniques.
- Strong collaboration, communication, and problem-solving skills, with the ability to work effectively in a team environment.
Join us in shaping the future of computing. Apply today to be part of Intel's mission to deliver exceptional technology that transforms the way the world lives, works, and connects.
Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research.
Benefits at Intel
Our total rewards package goes above and beyond just a paycheck. Whether you're looking to build your career, improve your health, or protect your wealth, we offer generous benefits to help you achieve your goals. Go to Intel Benefits | Intel Careers for details of benefits available to you. Intel reserves the right to modify, change or discontinue benefit plans at any time in its sole discretion.
Job Type:College GradShift:Shift 1 (United States of America)Primary Location: US, Texas, AustinAdditional Locations:US, Arizona, Phoenix, US, Oregon, HillsboroPosting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of TrustN/ABenefitsWe offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.
Annual Salary Range for jobs which could be performed in the US: $91,150.00-172,860.00 USDThe range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.Work Model for this Role
This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.*
ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.Sourced by ZipRecruiter
Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore's Law to bring smart, connected devices to every person on Earth
Manufacturing
10,000+ Employees
Santa Clara, CA, US
1968