RTL Design Engineer
$105K - $200K/yr
Develops the logic design, register transfer level (RTL) coding, and simulation for a CPU required ... Electrical or Computer Engineering or any STEM related education with at least 2+ years of ...
RTL Design Engineer
$105K - $200K/yr
Develops the logic design, register transfer level (RTL) coding, and simulation for a CPU required ... Electrical or Computer Engineering or any STEM related education with at least 2+ years of ...
RTL Design Engineer
Chandler, AZ · On-site
$127K - $203K/yr
Broadcom's Central Engineering Group is seeking a candidate to lead the digital design and ... Design convergence to timing closure utilizing RTL optimization strategies. * Conduct formal ...
RTL Design Engineer
Chandler, AZ · On-site
$127K - $203K/yr
Broadcom's Central Engineering Group is seeking a candidate to lead the digital design and ... Design convergence to timing closure utilizing RTL optimization strategies. * Conduct formal ...
RTL Design Engineer
$127K - $203K/yr
Broadcom's Central Engineering Group is seeking a candidate to lead the digital design and ... Design convergence to timing closure utilizing RTL optimization strategies. * Conduct formal ...
RTL Design Engineer
$127K - $203K/yr
Broadcom's Central Engineering Group is seeking a candidate to lead the digital design and ... Design convergence to timing closure utilizing RTL optimization strategies. * Conduct formal ...
CPU RTL Design Engineer
$141K - $269K/yr
As a CPU Logic Design Engineer, you will play a critical role in designing and optimizing the logic for Intel's cutting-edge processors. You will drive the development of register transfer level (RTL ...
CPU RTL Design Engineer
$141K - $269K/yr
As a CPU Logic Design Engineer, you will play a critical role in designing and optimizing the logic for Intel's cutting-edge processors. You will drive the development of register transfer level (RTL ...
Senior CPU RTL Design Engineer - Power Management
$164K - $269K/yr
As a Senior CPU RTL Design Engineer - Power Management , you will play a critical role in designing and delivering CPU microarchitectures with strong emphasis on power management and energy-efficient ...
Senior CPU RTL Design Engineer - Power Management
$164K - $269K/yr
As a Senior CPU RTL Design Engineer - Power Management , you will play a critical role in designing and delivering CPU microarchitectures with strong emphasis on power management and energy-efficient ...
As a Principal Digital Design Engineer, the candidate shall be working with multi-sited global ... RTL design, design verification, synthesis, STA, and Test using an industry leading ASIC design ...
As a Principal Digital Design Engineer, the candidate shall be working with multi-sited global ... RTL design, design verification, synthesis, STA, and Test using an industry leading ASIC design ...
As a Principal Digital Design Engineer, the candidate shall be working with multi-sited global ... RTL design, design verification, synthesis, STA, and Test using an industry leading ASIC design ...
As a Principal Digital Design Engineer, the candidate shall be working with multi-sited global ... RTL design, design verification, synthesis, STA, and Test using an industry leading ASIC design ...
Digital Design Engineer
Chandler, AZ · On-site
$133K/yr
Develop RTL designs using Verilog and support integration into larger SoC environments. * Design ... Exposure to low-power and high-performance ASIC design techniques. * Experience with back-end flows ...
Digital Design Engineer
Chandler, AZ · On-site
$133K/yr
Develop RTL designs using Verilog and support integration into larger SoC environments. * Design ... Exposure to low-power and high-performance ASIC design techniques. * Experience with back-end flows ...
Staff Digital Design Engineer
Chandler, AZ · On-site
$133K/yr
Develop RTL designs using Verilog and support integration into larger SoC environments. * Design ... Exposure to low-power and high-performance ASIC design techniques. * Experience with back-end flows ...
Staff Digital Design Engineer
Chandler, AZ · On-site
$133K/yr
Develop RTL designs using Verilog and support integration into larger SoC environments. * Design ... Exposure to low-power and high-performance ASIC design techniques. * Experience with back-end flows ...
Senior Digital Design Engineer
Chandler, AZ · On-site
$133K/yr
Develop RTL designs using Verilog and support integration into larger SoC environments. * Design ... Exposure to low-power and high-performance ASIC design techniques. * Experience with back-end flows ...
Senior Digital Design Engineer
Chandler, AZ · On-site
$133K/yr
Develop RTL designs using Verilog and support integration into larger SoC environments. * Design ... Exposure to low-power and high-performance ASIC design techniques. * Experience with back-end flows ...
FPGA Design Engineer
Tucson, AZ · On-site
$116K - $160K/yr
Develop RTL and support simulation, synthesis, place and route, timing closure, hardware ... Computer Engineering, or a related technical field. * 8+ years of professional FPGA design and ...
FPGA Design Engineer
Tucson, AZ · On-site
$116K - $160K/yr
Develop RTL and support simulation, synthesis, place and route, timing closure, hardware ... Computer Engineering, or a related technical field. * 8+ years of professional FPGA design and ...
FPGA Design Engineer
Tucson, AZ · On-site
$116K - $160K/yr
Develop RTL and support simulation, synthesis, place and route, timing closure, hardware ... Computer Engineering, or a related technical field. * 8+ years of professional FPGA design and ...
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FPGA Design Engineer
Tucson, AZ · On-site
$116K - $160K/yr
Develop RTL and support simulation, synthesis, place and route, timing closure, hardware ... Computer Engineering, or a related technical field. * 8+ years of professional FPGA design and ...
FPGA Design Engineer
$116K - $160K/yr
Develop RTL and support simulation, synthesis, place and route, timing closure, hardware ... Computer Engineering, or a related technical field. * 8+ years of professional FPGA design and ...
FPGA Design Engineer
$116K - $160K/yr
Develop RTL and support simulation, synthesis, place and route, timing closure, hardware ... Computer Engineering, or a related technical field. * 8+ years of professional FPGA design and ...
Senior Staff Digital Design Engineer
Chandler, AZ · On-site
$133K/yr
Develop RTL designs using Verilog and support integration into larger SoC environments. * Design ... Exposure to low-power and high-performance ASIC design techniques. * Experience with back-end flows ...
Senior Staff Digital Design Engineer
Chandler, AZ · On-site
$133K/yr
Develop RTL designs using Verilog and support integration into larger SoC environments. * Design ... Exposure to low-power and high-performance ASIC design techniques. * Experience with back-end flows ...
We are seeking a Senior Engineer I - design to join our team. This role involves RTL design ... optimize RTL (Verilog/SystemVerilog) for digital blocks and subsystems targeting ASIC ...
We are seeking a Senior Engineer I - design to join our team. This role involves RTL design ... optimize RTL (Verilog/SystemVerilog) for digital blocks and subsystems targeting ASIC ...
Senior Engineer I- Design
Chandler, AZ · On-site
We are seeking a Senior Engineer I - design to join our team. This role involves RTL design ... optimize RTL (Verilog/SystemVerilog) for digital blocks and subsystems targeting ASIC ...
Senior Engineer I- Design
Chandler, AZ · On-site
We are seeking a Senior Engineer I - design to join our team. This role involves RTL design ... optimize RTL (Verilog/SystemVerilog) for digital blocks and subsystems targeting ASIC ...
This is a hands-on role spanning RTL design, integration, and signoff verification-with broad cross ... ASIC/SoC Digital Design and Verification * Strong foundations in digital logic / finite state ...
This is a hands-on role spanning RTL design, integration, and signoff verification-with broad cross ... ASIC/SoC Digital Design and Verification * Strong foundations in digital logic / finite state ...
Principal Engineer-Design
Chandler, AZ · On-site
This is a hands-on role spanning RTL design, integration, and signoff verification-with broad cross ... ASIC/SoC Digital Design and Verification * Strong foundations in digital logic / finite state ...
Principal Engineer-Design
Chandler, AZ · On-site
This is a hands-on role spanning RTL design, integration, and signoff verification-with broad cross ... ASIC/SoC Digital Design and Verification * Strong foundations in digital logic / finite state ...
Principal Digital Design Engineer
Chandler, AZ · On-site +1
$200K - $250K/yr
Head of Engineering About Us PowerLattice is a well-funded semiconductor start-up company backed by ... Actively contribute to RTL development for key components * Drive design tradeoffs across ...
Principal Digital Design Engineer
Chandler, AZ · On-site +1
$200K - $250K/yr
Head of Engineering About Us PowerLattice is a well-funded semiconductor start-up company backed by ... Actively contribute to RTL development for key components * Drive design tradeoffs across ...
Staff Digital Design Engineer
Chandler, AZ · On-site
$133K/yr
... Engineer to join our growing hardware development team in Chandler, AZ. In this role, you will be ... RTL for digital CMOS circuit design. • Strong understanding of ASIC design methodology. • ...
Staff Digital Design Engineer
Chandler, AZ · On-site
$133K/yr
... Engineer to join our growing hardware development team in Chandler, AZ. In this role, you will be ... RTL for digital CMOS circuit design. • Strong understanding of ASIC design methodology. • ...
Locum Asic Rtl Design Engineer information
What is the difference between Locum Asic Rtl Design Engineer vs Contract Asic Rtl Design Engineer?
| Aspect | Locum Asic Rtl Design Engineer | Contract Asic Rtl Design Engineer |
|---|---|---|
| Credentials | Typically requires relevant engineering degrees and RTL design experience | Similar credentials, often with specific RTL design certifications |
| Work Environment | Temporary, short-term assignments often in multiple locations | Project-based roles, usually in a fixed location or remote |
| Employer Usage | Used by agencies or companies needing immediate, short-term expertise | Engaged by companies or staffing agencies for project-specific work |
Both roles involve RTL design skills for ASIC development, but a Locum Asic Rtl Design Engineer typically fills short-term, temporary positions, often through staffing agencies, while a Contract Asic Rtl Design Engineer is engaged for specific projects with defined durations. The main difference lies in the nature and duration of employment, but both require similar technical credentials and work environments.
What are the most commonly searched types of Asic Rtl Design Engineer jobs in Arizona? The most popular types of Asic Rtl Design Engineer jobs in Arizona are:
What are popular job titles related to Locum Asic Rtl Design Engineer jobs in Arizona? For Locum Asic Rtl Design Engineer jobs in Arizona, the most frequently searched job titles are:
What job categories do people searching Locum Asic Rtl Design Engineer jobs in Arizona look for? The top searched job categories for Locum Asic Rtl Design Engineer jobs in Arizona are:
What cities in Arizona are hiring for Locum Asic Rtl Design Engineer jobs? Cities in Arizona with the most Locum Asic Rtl Design Engineer job openings:
$105K - $200K/yr
Full-time
Medical, Retirement, PTO
Posted 7 days ago
Intel rating
8.7
Based on 147 frontline employees who took The Breakroom Quiz
19th of 156 rated electronics manufacturers
Job description
Job Details:Job Description: Develops the logic design, register transfer level (RTL) coding, and simulation for a CPU required to generate cell libraries, functional units, and the CPU IP block for integration in full chip designs. Participates actively in the definition of architecture and microarchitecture features of the CPU being designed. Applies various strategies, tools, and methods to write RTL and optimize logic to qualify the design to meet power, performance, area, and timing goals as well as design integrity for physical implementation. Reviews the verification plan and implementation to ensure design features are verified correctly and resolves and implements corrective measures for failing RTL tests to ensure correctness of features. Documents micro architectural specs (MAS) of the CPU features being designed. Supports SoC customers to ensure highquality integration of the CPU block.Qualifications:Minimum QualificationsThe candidate must have a Bachelor's Degree in Electrical or Computer Engineering or any STEM related education with at least 2+ years of experience -OR- Master's Degree in Electrical or Computer EngineeringAt least 1+ years of coursework or experience in the following areas:oBasic Logic DesignoMicroprocessorsoComputer ArchitectureoDigital design and RTL codingoVerilog/SystemVerilog and/or VHDLoSynthesis tools (Design Compiler, Genus)oScripting languages (Python, Perl, TCL)Preferred QualificationsExperience with advanced verification methodologies (UVM, OVM)Knowledge of low-power design techniquesUnderstanding of physical design constraints and timing closureExperience with version control systems (Git, Perforce)Experience with simulation tools (ModelSim, VCS, Xcelium)Job Type:College GradShift:Shift 1 (United States of America)Primary Location: US, Texas, AustinAdditional Locations:US, Arizona, Phoenix, US, Oregon, HillsboroPosting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of TrustN/ABenefits
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.
Annual Salary Range for jobs which could be performed in the US: $105,650.00-200,340.00 USDThe range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.Work Model for this Role
This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.*
ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.
About Intel
Sourced by ZipRecruiter
Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore's Law to bring smart, connected devices to every person on Earth
Industry
Manufacturing
Company size
10,000+ Employees
Headquarters location
Santa Clara, CA, US
Year founded
1968