Bachelor's degree in Electrical Engineering, Computer Engineering, or a related technical field. * 12+ years of semiconductor, ASIC, SoC, foundry, IP, or complex silicon solution sales experience ...
Bachelor's degree in Electrical Engineering, Computer Engineering, or a related technical field. * 12+ years of semiconductor, ASIC, SoC, foundry, IP, or complex silicon solution sales experience ...
Senior FPGA Design Engineer
Chandler, AZ · On-site
$101.10K - $136.10K/yr
Strong digital design engineer with FPGA/ASIC SoC design experience * Strong FPGA Implementation with Altera Quartus or Xilinx Vivado * Experience designing/debugging SoC systems with AMBA-compliant ...
Quick apply
Senior FPGA Design Engineer
Chandler, AZ · On-site
$101.10K - $136.10K/yr
Strong digital design engineer with FPGA/ASIC SoC design experience * Strong FPGA Implementation with Altera Quartus or Xilinx Vivado * Experience designing/debugging SoC systems with AMBA-compliant ...
Senior FPGA Engineer with Security Clearance
$101.10K - $136.10K/yr
Qualifications • Strong digital design engineer with FPGA/ASIC SoC design experience • Strong FPGA Implementation with Altera Quartus or Xilinx Vivado • Experience designing/debugging SoC ...
Senior FPGA Engineer with Security Clearance
$101.10K - $136.10K/yr
Qualifications • Strong digital design engineer with FPGA/ASIC SoC design experience • Strong FPGA Implementation with Altera Quartus or Xilinx Vivado • Experience designing/debugging SoC ...
Physical Design Engineer
Phoenix, AZ · On-site
$135K - $139K/yr
... ASIC/SoC design Min. * Qualifications: 0-1 yrs of exp. Enginner - CL11 & CL10 Master's degree in Electrical Eng. or Comp. Science RTL2GDSII exp. on advanced tech. nodes (7nm and below) Exp. w/low ...
Physical Design Engineer
Phoenix, AZ · On-site
$135K - $139K/yr
... ASIC/SoC design Min. * Qualifications: 0-1 yrs of exp. Enginner - CL11 & CL10 Master's degree in Electrical Eng. or Comp. Science RTL2GDSII exp. on advanced tech. nodes (7nm and below) Exp. w/low ...
Position Overview We seek a Senior ASIC Design Engineer to provide technical support to Intel ... domain in SoC design * Experience using EDA tools for multi-power domain design (UPF/CPF ...
Position Overview We seek a Senior ASIC Design Engineer to provide technical support to Intel ... domain in SoC design * Experience using EDA tools for multi-power domain design (UPF/CPF ...
Position Overview We seek a Senior ASIC Design Engineer to provide technical support to Intel ... domain in SoC design * Experience using EDA tools for multi-power domain design (UPF/CPF ...
Position Overview We seek a Senior ASIC Design Engineer to provide technical support to Intel ... domain in SoC design * Experience using EDA tools for multi-power domain design (UPF/CPF ...
Principal Engineer-Design
Chandler, AZ · On-site
S. in Electrical Engineering, Computer Engineering, or related field with 10+ years' experience in ASIC/SoC Digital Design and Verification * Strong foundations in digital logic / finite state ...
Principal Engineer-Design
Chandler, AZ · On-site
S. in Electrical Engineering, Computer Engineering, or related field with 10+ years' experience in ASIC/SoC Digital Design and Verification * Strong foundations in digital logic / finite state ...
Principal Engineer-Design
Chandler, AZ · On-site
S. in Electrical Engineering, Computer Engineering, or related field with 10+ years' experience in ASIC/SoC Digital Design and Verification * Strong foundations in digital logic / finite state ...
Principal Engineer-Design
Chandler, AZ · On-site
S. in Electrical Engineering, Computer Engineering, or related field with 10+ years' experience in ASIC/SoC Digital Design and Verification * Strong foundations in digital logic / finite state ...
... ASIC/SOC development life cycle Understanding and/or hands-on experience in design, test, quality and product engineering. Ability to scope and manage complex projects timing and budget spanning ...
... ASIC/SOC development life cycle Understanding and/or hands-on experience in design, test, quality and product engineering. Ability to scope and manage complex projects timing and budget spanning ...
Program Manager
Chandler, AZ · On-site
... ASIC/SOC development life cycle • Understanding and/or hands-on experience in design, test, quality and product engineering. • Ability to scope and manage complex projects timing and budget ...
Program Manager
Chandler, AZ · On-site
... ASIC/SOC development life cycle • Understanding and/or hands-on experience in design, test, quality and product engineering. • Ability to scope and manage complex projects timing and budget ...
... ASIC/SOC development life cycle • Understanding and/or hands-on experience in design, test, quality and product engineering. • Ability to scope and manage complex projects timing and budget ...
Quick apply
... ASIC/SOC development life cycle • Understanding and/or hands-on experience in design, test, quality and product engineering. • Ability to scope and manage complex projects timing and budget ...
SOC Physical Design Static Timing Analysis Engineer
Phoenix, AZ · On-site
$164.47K - $311.89K/yr
Perform SOC level timing analysis and optimization, ensuring designs meet functional and ... Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom ...
SOC Physical Design Static Timing Analysis Engineer
Phoenix, AZ · On-site
$164.47K - $311.89K/yr
Perform SOC level timing analysis and optimization, ensuring designs meet functional and ... Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom ...
SOC Physical Design Static Timing Analysis Engineer
$164.47K - $311.89K/yr
Perform SOC level timing analysis and optimization, ensuring designs meet functional and ... Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom ...
SOC Physical Design Static Timing Analysis Engineer
$164.47K - $311.89K/yr
Perform SOC level timing analysis and optimization, ensuring designs meet functional and ... Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom ...
DFT Application Engineer
Phoenix, AZ · On-site
Drive quality improvements in ASIC DFT/DFM and ATPG validation methodology, capability/flow, and documentation for both block-level and SoC-level implementations * Collaborate with RTL and Hard IP ...
DFT Application Engineer
Phoenix, AZ · On-site
Drive quality improvements in ASIC DFT/DFM and ATPG validation methodology, capability/flow, and documentation for both block-level and SoC-level implementations * Collaborate with RTL and Hard IP ...
DFT Application Engineer
Phoenix, AZ · On-site
Drive quality improvements in ASIC DFT/DFM and ATPG validation methodology, capability/flow, and documentation for both block-level and SoC-level implementations * Collaborate with RTL and Hard IP ...
DFT Application Engineer
Phoenix, AZ · On-site
Drive quality improvements in ASIC DFT/DFM and ATPG validation methodology, capability/flow, and documentation for both block-level and SoC-level implementations * Collaborate with RTL and Hard IP ...
DFT Application Engineer
Chandler, AZ · On-site
... ASIC DFT/DFM and ATPG validation methodology, capability/flow, and documentation for both block-level and SoC-level implementations - Collaborate with RTL and Hard IP designers on DFT/DFM ...
DFT Application Engineer
Chandler, AZ · On-site
... ASIC DFT/DFM and ATPG validation methodology, capability/flow, and documentation for both block-level and SoC-level implementations - Collaborate with RTL and Hard IP designers on DFT/DFM ...
... ASIC design signoff (SoC/ASIC) * 3+ yearsofexperienceinone of the followingscripting languages (i.e.Python, Perl,Tcl, shell scripting) Preferred Qualifications * Active US Government Security ...
... ASIC design signoff (SoC/ASIC) * 3+ yearsofexperienceinone of the followingscripting languages (i.e.Python, Perl,Tcl, shell scripting) Preferred Qualifications * Active US Government Security ...
... SoC/ASIC) * 3+ years of experience in one of the following scripting languages (i.e. Python, Perl, Tcl, shell scripting) Preferred Qualifications * Active US Government Security Clearance with a ...
... SoC/ASIC) * 3+ years of experience in one of the following scripting languages (i.e. Python, Perl, Tcl, shell scripting) Preferred Qualifications * Active US Government Security Clearance with a ...
FPGA VHDL Design Engineer US Citizenship required
$116.30K - $160.30K/yr
... ASIC development design flows and methodologies for SOC design - Use of VHDL and Verilog - Use of ARM processor cores and associated peripherals - ASIC supplier management and technical oversight ...
FPGA VHDL Design Engineer US Citizenship required
$116.30K - $160.30K/yr
... ASIC development design flows and methodologies for SOC design - Use of VHDL and Verilog - Use of ARM processor cores and associated peripherals - ASIC supplier management and technical oversight ...
FPGA VHDL Design Engineer US Citizenship required
Tucson, AZ · On-site
$116.30K - $160.30K/yr
... ASIC development design flows and methodologies for SOC design - Use of VHDL and Verilog - Use of ARM processor cores and associated peripherals - ASIC supplier management and technical oversight ...
FPGA VHDL Design Engineer US Citizenship required
Tucson, AZ · On-site
$116.30K - $160.30K/yr
... ASIC development design flows and methodologies for SOC design - Use of VHDL and Verilog - Use of ARM processor cores and associated peripherals - ASIC supplier management and technical oversight ...
Asic Soc information
What is the difference between Asic Soc vs FPGA Designer?
| Aspect | Asic Soc | FPGA Designer |
|---|---|---|
| Required Skills | Hardware design, embedded systems, VHDL/Verilog, ASIC development | Hardware description languages, FPGA architecture, VHDL/Verilog |
| Work Environment | Semiconductor companies, integrated circuit design labs | Electronics firms, prototyping labs, FPGA development environments |
| Industry Usage | Consumer electronics, automotive, telecommunications | Prototyping, testing, low-volume production |
Both Asic Soc and FPGA Designer roles involve hardware description languages and embedded systems, but Asic Soc engineers focus on designing integrated circuits for mass production, while FPGA Designers work on flexible, reprogrammable hardware for testing and prototyping. The skills overlap makes them common choices for hardware development in electronics industries.
What are popular job titles related to Asic Soc jobs in Arizona? For Asic Soc jobs in Arizona, the most frequently searched job titles are:
- Remote Work From Home Analog Mixed Signal Design Engineer
- Analog Mixed Signal Verification
- Asic Engineer
- Senior Asic Design Engineer
- Design Verification Engineer
- Asic Design
- Freelance Asic Verification Engineer
- Freelance Fpga Verification Engineer
- Asic Verification Engineer Remote
- Work From Home Rf Ic Design Engineer
What job categories do people searching Asic Soc jobs in Arizona look for? The top searched job categories for Asic Soc jobs in Arizona are:
What cities in Arizona are hiring for Asic Soc jobs? Cities in Arizona with the most Asic Soc job openings:
Full-time
Medical, Retirement, PTO
Posted 14 days ago
Intel rating
8.8
Based on 143 frontline employees who took The Breakroom Quiz
9th of 137 rated electronics manufacturers
Job description
Job Details:Job Description:
Intel is seeking a highly strategic Custom ASIC Sales Leader to build a global team of expert custom silicon and ASIC sales specialists focused on identifying, shaping, and winning custom opportunities with our largest and most strategic customers. This leader will define and execute a worldwide go-to-market motion for custom silicon engagements, align deeply with customer roadmaps, and translate complex market requirements into high-value custom silicon business opportunities for Intel.
The leader is expected to drive account planning and execution aligned with customer priorities and Intel's long-term growth objectives; consistent with Intel sales leadership expectations. This position is ideally located in the Bay Area in California, other locations may be considered based on candidate fit and business need.
Key Responsibilities
- Build, lead, and develop a high-performing global sales team of custom silicon sales specialists covering Intel's largest and most strategic accounts and opportunities.
- Define the global strategy for customer identification, prioritization, pursuit, and conversion of custom opportunities across targeted market segments.
- Establish executive-level relationships with key decision-makers across hyper-scalers, OEMs, automotive, communications, and other large-scale silicon buyers.
- Drive account planning and execution aligned to both customer priorities and Intel's long-term growth objectives.
- Partner closely with key internal partners and the executive leadership team to shape competitive, scalable, and profitable custom solutions.
- Lead complex deal strategy across long sales cycles, including customer discovery, solution definition, commercial negotiation, internal investment alignment, and business case development.
- Develop a disciplined global opportunity pipeline, forecast accuracy model, and governance cadence for custom silicon pursuits.
- Bring external market intelligence, competitive insight, and customer feedback into Intel's strategic planning and portfolio decisions.
- Influence internal roadmaps and engagement models to improve Intel's competitiveness in the custom ASIC and IC market.
- Serve as a senior external and internal ambassador for Intel's custom silicon portfolio.
- Demonstrated experience selling into large global customers and driving strategic account growth.
- Proven success managing long-cycle, highly technical, multi-stakeholder sales pursuits.
- Strong semiconductor industry network with pre-existing executive relationships, a common requirement in advanced semiconductor sales leadership roles.
Additional Job Requirements
- Deep knowledge of the ASIC market landscape, including customer decision criteria, competitive dynamics, and ecosystem partners; ASIC sales roles typically require strong technical semiconductor knowledge.
- Extensive network across the ASIC and broader semiconductor ecosystem, including IC design firms, platform companies, and enterprise technology buyers.
- Exceptional executive communication, negotiation, and selling skills.
- Strong financial and business acumen, including investment case development, margin analysis, and opportunity qualification.
- Ability to travel globally as needed to support customers, internal stakeholders, and team development.
- Ability to operate effectively in a matrixed, cross-functional, and fast-evolving business environment.
- High degree of strategic judgment, ownership, and bias for action.
- Comfortable with ambiguity and able to build structure, talent, and process in a growth-oriented environment.
Leadership Expectations
The successful candidate will be a builder, strategist, and enterprise leader. This person must combine external market credibility with internal cross-functional influence, and must be capable of creating a global operating rhythm that scales Intel ASIC opportunity creation and rapidly accelerates win rates across the globe. The role requires a leader who can hire exceptional talent, coach experienced sellers, and shape Intel's long-term position in the custom ASIC market.
Qualifications:Minimum Qualifications
- Bachelor's degree in Electrical Engineering, Computer Engineering, or a related technical field.
- 12+ years of semiconductor, ASIC, SoC, foundry, IP, or complex silicon solution sales experience.
- 5+ years of people management experience, including leading senior or specialist sales talent.
Preferred Qualifications
- MBA or advanced technical degree.
- Direct experience in custom ASIC, semi-custom silicon, foundry services, design services, or related silicon commercialization models.
- Experience working with hyperscale, cloud, data center, networking, automotive, or high-performance computing customers and executives.
- Strong understanding of semiconductor business models, including NRE structures, wafer supply considerations, packaging, yield, roadmap alignment, and lifecycle support.
- Experience building or scaling geographically distributed sales teams.
- Demonstrated ability to influence C-level and SVP-level stakeholders internally and externally.
- Track record of negotiating complex strategic agreements and structuring large, multi-year opportunities.
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.
Annual Salary Range for jobs which could be performed in the US: $454,230.00-641,270.00 USDThe range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.*
ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.
About Intel
Sourced by ZipRecruiter
Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore's Law to bring smart, connected devices to every person on Earth
Industry
Manufacturing
Company size
10,000+ Employees
Headquarters location
Santa Clara, CA, US
Year founded
1968