Senior Design Verification Engineer
$176K - $264K/yr
You will be asked to help evaluate and deploy new technologies for design verification as they ... ASIC designs. You will be responsible for: * Design verification planning including test plans
$176K - $264K/yr
You will be asked to help evaluate and deploy new technologies for design verification as they ... ASIC designs. You will be responsible for: * Design verification planning including test plans
$176K - $264K/yr
You will be asked to help evaluate and deploy new technologies for design verification as they ... ASIC designs. You will be responsible for: * Design verification planning including test plans
Tempe, AZ · On-site
$176K - $264K/yr
You will be asked to help evaluate and deploy new technologies for design verification as they ... ASIC designs. You will be responsible for: * Design verification planning including test plans
Tempe, AZ · On-site
$176K - $264K/yr
You will be asked to help evaluate and deploy new technologies for design verification as they ... ASIC designs. You will be responsible for: * Design verification planning including test plans
Chandler, AZ · On-site
$133K - $163K/yr
For over four decades, Cirrus Logic has been propelled by the top engineers in mixed-signal ... Significant industry experience in silicon design and/or ASIC verification. * Strong proficiency ...
Chandler, AZ · On-site
$133K - $163K/yr
For over four decades, Cirrus Logic has been propelled by the top engineers in mixed-signal ... Significant industry experience in silicon design and/or ASIC verification. * Strong proficiency ...
Tucson, AZ · On-site
$128K - $156K/yr
We are looking for a Sr. Design Verification Engineer for our company in Tucson, AZ ... Responsible for all test software required to verify a SOC ASIC. * May include integrating new ...
Tucson, AZ · On-site
$128K - $156K/yr
We are looking for a Sr. Design Verification Engineer for our company in Tucson, AZ ... Responsible for all test software required to verify a SOC ASIC. * May include integrating new ...
Chandler, AZ · On-site
$133K - $163K/yr
For over four decades, Cirrus Logic has been propelled by the top engineers in mixed-signal ... Significant industry experience in silicon design and/or ASIC verification * Strong proficiency ...
Chandler, AZ · On-site
$133K - $163K/yr
For over four decades, Cirrus Logic has been propelled by the top engineers in mixed-signal ... Significant industry experience in silicon design and/or ASIC verification * Strong proficiency ...
Chandler, AZ · On-site
$133K - $163K/yr
For over four decades, Cirrus Logic has been propelled by the top engineers in mixed-signal ... Significant industry experience in silicon design and/or ASIC verification. * Strong proficiency ...
Chandler, AZ · On-site
$133K - $163K/yr
For over four decades, Cirrus Logic has been propelled by the top engineers in mixed-signal ... Significant industry experience in silicon design and/or ASIC verification. * Strong proficiency ...
Tempe, AZ · On-site
$176K - $264K/yr
You will be asked to help evaluate and deploy new technologies for design verification as they ... ASIC designs. You will be responsible for: * Design verification planning including test plans
Tempe, AZ · On-site
$176K - $264K/yr
You will be asked to help evaluate and deploy new technologies for design verification as they ... ASIC designs. You will be responsible for: * Design verification planning including test plans
$141K - $200K/yr
Join Intel as a Mixed Signal Design Verification Engineer and play a critical role in shaping the ... Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom ...
$141K - $200K/yr
Join Intel as a Mixed Signal Design Verification Engineer and play a critical role in shaping the ... Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom ...
Phoenix, AZ · On-site
$141K - $200K/yr
Join Intel as a Mixed Signal Design Verification Engineer and play a critical role in shaping the ... Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom ...
Phoenix, AZ · On-site
$141K - $200K/yr
Join Intel as a Mixed Signal Design Verification Engineer and play a critical role in shaping the ... Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom ...
Chandler, AZ · On-site
$133K - $163K/yr
For over four decades, Cirrus Logic has been propelled by the top engineers in mixed-signal ... Significant industry experience in silicon design and/or ASIC verification. * Strong proficiency ...
Chandler, AZ · On-site
$133K - $163K/yr
For over four decades, Cirrus Logic has been propelled by the top engineers in mixed-signal ... Significant industry experience in silicon design and/or ASIC verification. * Strong proficiency ...
$172K - $199K/yr
Define and verify interfaces, state machines, and controlling logic required to implement new ... Design Verification Engineer or related occupation performing module level design performing with ...
$172K - $199K/yr
Define and verify interfaces, state machines, and controlling logic required to implement new ... Design Verification Engineer or related occupation performing module level design performing with ...
Chandler, AZ · On-site
$172K - $199K/yr
Define and verify interfaces, state machines, and controlling logic required to implement new ... Design Verification Engineer or related occupation performing module level design performing with ...
Chandler, AZ · On-site
$172K - $199K/yr
Define and verify interfaces, state machines, and controlling logic required to implement new ... Design Verification Engineer or related occupation performing module level design performing with ...
... ASIC design implementing and verification in area of low power, multi-voltage domain * 3+ years of ... The Central Engineering Group (CEG) is Intel's data-driven organization that builds scalable ...
... ASIC design implementing and verification in area of low power, multi-voltage domain * 3+ years of ... The Central Engineering Group (CEG) is Intel's data-driven organization that builds scalable ...
... ASIC design implementing and verification in area of low power, multi-voltage domain * 3+ years of ... The Central Engineering Group (CEG) is Intel's data-driven organization that builds scalable ...
... ASIC design implementing and verification in area of low power, multi-voltage domain * 3+ years of ... The Central Engineering Group (CEG) is Intel's data-driven organization that builds scalable ...
What will you do as our Senior Design Verification Engineer? The Senior Engineer role has the ... Able to take ownership of the testing of new product features, analyze use cases and create ...
What will you do as our Senior Design Verification Engineer? The Senior Engineer role has the ... Able to take ownership of the testing of new product features, analyze use cases and create ...
What will you do as our Senior Design Verification Engineer? The Senior Engineer role has the ... Able to take ownership of the testing of new product features, analyze use cases and create ...
What will you do as our Senior Design Verification Engineer? The Senior Engineer role has the ... Able to take ownership of the testing of new product features, analyze use cases and create ...
Tucson, AZ · On-site
$116K - $142K/yr
Texas Instruments' Precision ADC team is seeking a Design Verification Engineer to help verify ... Ability to quickly ramp on new systems and processes About Us Why TI? * Engineer your future. We ...
Tucson, AZ · On-site
$116K - $142K/yr
Texas Instruments' Precision ADC team is seeking a Design Verification Engineer to help verify ... Ability to quickly ramp on new systems and processes About Us Why TI? * Engineer your future. We ...
$116K - $142K/yr
Texas Instruments' Precision ADC team is seeking a Design Verification Engineer to help verify ... Ability to quickly ramp on new systems and processes
$116K - $142K/yr
Texas Instruments' Precision ADC team is seeking a Design Verification Engineer to help verify ... Ability to quickly ramp on new systems and processes
Tucson, AZ · On-site
$116K - $142K/yr
As a Mixed-signal Design Verification Engineer in the DAC team, you will be responsible for ... Ability to quickly ramp on new systems and processes * Demonstrated strong interpersonal ...
Tucson, AZ · On-site
$116K - $142K/yr
As a Mixed-signal Design Verification Engineer in the DAC team, you will be responsible for ... Ability to quickly ramp on new systems and processes * Demonstrated strong interpersonal ...
As a Principal Digital Design Engineer, the candidate shall be working with multi-sited global ... verification, synthesis, STA, and Test using an industry leading ASIC design flow. Candidate must ...
As a Principal Digital Design Engineer, the candidate shall be working with multi-sited global ... verification, synthesis, STA, and Test using an industry leading ASIC design flow. Candidate must ...
| Aspect | New Grad Asic Design Verification Engineer | New Grad Digital Design Engineer |
|---|---|---|
| Required Skills | Hardware verification, simulation, scripting, HDL knowledge | Digital circuit design, HDL coding, logic design |
| Work Environment | Verification labs, simulation tools, hardware testing | Design teams, FPGA/ASIC development, coding |
| Industry Usage | Primarily in semiconductor and chip companies | Broadly in electronics, semiconductor, and tech firms |
While both roles require HDL knowledge and work in semiconductor environments, the New Grad Asic Design Verification Engineer focuses on verifying and testing ASIC designs, whereas the New Grad Digital Design Engineer is involved in designing digital circuits. Both roles are essential in chip development but differ in their primary responsibilities and skill emphasis.
6.3
Based on 11 frontline employees who took The Breakroom Quiz
79th of 96 rated telecommunications companies
One team. Global challenges. Infinite opportunities. At Viasat, we’re on a mission to deliver connections with the capacity to change the world. For more than 35 years, Viasat has helped shape how consumers, businesses, governments and militaries around the globe communicate. We’re looking for people who think big, act fearlessly, and create an inclusive environment that drives positive impact to join our team.
At Viasat, you will be joining a talented and motivated team of systems engineers, design engineers, and design verification engineers developing cutting edge communications technology with a focus on high quality and time to market.
You will be working in a verification environment utilizing current tools and methodologies such as Universal Verification Methodology (UVM) and new DV AI agentic tools. You will be asked to help evaluate and deploy new technologies for design verification as they become available.
As a Design Verification Engineer, you will be part of a verification team responsible for the full cycle of RTL verification for FPGA and ASIC designs. You will be responsible for:
Architecting Design Verification environments for ASICs and FPGAs.
Working with RTL, System and software engineers to determine appropriate coverage closure for chip designs.
Create drivers, monitors, scoreboards, sequences, and model predictors for a variety of interfaces and designs.
Maintaining and communicating program schedule and task tracking (Agile Jira based).
Debugging failing tests, understanding both the UVM testbench and VHDL/Verilog source code, working closely with the RTL developers.
Experience in UVM testbench creation and usage
Bachelor's Degree in Electrical Engineering, Computer Engineering or a related field
Experience with AI and agentic flow methodologies for design verification and chip development
Foundational knowledge of digital logic and timing considerations
Attention to detail, ability to follow process and coding guidelines, participate in code reviews and accept feedback
Experience with industry standard simulators such as Questa, Xcelium and VCS
Proven track record of work in UVM testbench development
US citizenship
Ability to travel up to 10%
Strong written and verbal communication skills, ability to work with a geographically distributed team
Object oriented programming experience
Familiarity with designing and coding for testbench horizontal and vertical re-use
Familiarity with AI coding agents for design verificaiton
Ability to work independently, take initiative, and take ownership of tasks and results
#LI-AF1
Viasat is proud to be an equal opportunity employer, seeking to create a welcoming and diverse environment. All qualified applicants will receive consideration for employment without regard to race, color, religion, gender, gender identity or expression, sexual orientation, national origin, ancestry, physical or mental disability, medical condition, marital status, genetics, age, or veteran status or any other applicable legally protected status or characteristic. If you would like to request an accommodation on the basis of disability for completing this on-line application, please click here.
Qualifications:Experience in UVM testbench creation and usage
Bachelor's Degree in Electrical Engineering, Computer Engineering or a related field
Experience with AI and agentic flow methodologies for design verification and chip development
Foundational knowledge of digital logic and timing considerations
Attention to detail, ability to follow process and coding guidelines, participate in code reviews and accept feedback
Experience with industry standard simulators such as Questa, Xcelium and VCS
Proven track record of work in UVM testbench development
US citizenship
Ability to travel up to 10%
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At Viasat, we're on a mission to deliver connections with the capacity to change the world. For more than 35 years, Viasat has helped shape how consumers, businesses, governments and militaries around the globe communicate.
Telecommunications
5,001 - 10,000 Employees
Carlsbad, CA, US
1986