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New Grad Asic Design Verification Engineer Jobs in Arizona

Raytheon

Senior FPGA Design Engineer

Tucson, AZ

$116K - $160K/yr

Together, we push the boundaries of known science and find new ways to connect and protect our ... FPGA/ASIC design, including VHDL and/or Verilog coding or FPGA/ASIC verification using ...

Raytheon

Senior FPGA Design Engineer

Tucson, AZ

$116K - $160K/yr

Together, we push the boundaries of known science and find new ways to connect and protect our ... FPGA/ASIC design, including VHDL and/or Verilog coding or FPGA/ASIC verification using ...

Raytheon

Senior FPGA Design Engineer

Phoenix, AZ

$122K - $168K/yr

Together, we push the boundaries of known science and find new ways to connect and protect our ... FPGA/ASIC design, including VHDL and/or Verilog coding or FPGA/ASIC verification using ...

VertuCom

FPGA Engineer with Security Clearance

Tucson, AZ · On-site

$105K - $145K/yr

... new parts, collaborative modeling of algorithms, partition and perform code development, simulation ... design (VHDL coding) or FPGA/ASIC verification (SystemVerilog coding with UVM) • Xilinx or ...

Prattwhitney

Senior FPGA Design Engineer

Tucson, AZ · On-site

$86.80 - $165.20/hr

Lead small teams and mentor junior engineers. * Support internal and external technical reviews ... Experience with FPGA/ASIC design, including VHDL and/or Verilog coding or FPGA/ASIC verification ...

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New Grad Asic Design Verification Engineer information

What does a new grad ASIC design verification engineer do?

A New Grad ASIC Design Verification Engineer is responsible for testing and validating the design of Application-Specific Integrated Circuits (ASICs) to ensure they meet functional and performance specifications. They typically create testbenches, develop verification plans, write test cases using hardware description languages like SystemVerilog, and debug issues found during simulations. This role is crucial for catching design flaws before manufacturing, working closely with design engineers and using both manual and automated verification methods. As a new graduate, you will learn industry-standard verification methodologies and tools while contributing to the success of the silicon development process.

What are the key skills and qualifications needed to thrive as a new grad ASIC design verification engineer?

To thrive as a New Grad ASIC Design Verification Engineer, you need a solid understanding of digital design principles, hardware description languages (such as Verilog or VHDL), and a relevant degree in electrical or computer engineering. Familiarity with industry-standard verification tools and environments like SystemVerilog, UVM, and simulation/debugging platforms is typically required. Strong analytical thinking, attention to detail, and effective teamwork skills help you excel in diagnosing issues and collaborating with design teams. These skills and qualities ensure robust verification processes that lead to functional, reliable ASIC products.

What is the difference between New Grad Asic Design Verification Engineer vs New Grad Digital Design Engineer?

AspectNew Grad Asic Design Verification EngineerNew Grad Digital Design Engineer
Required SkillsHardware verification, simulation, scripting, HDL knowledgeDigital circuit design, HDL coding, logic design
Work EnvironmentVerification labs, simulation tools, hardware testingDesign teams, FPGA/ASIC development, coding
Industry UsagePrimarily in semiconductor and chip companiesBroadly in electronics, semiconductor, and tech firms

While both roles require HDL knowledge and work in semiconductor environments, the New Grad Asic Design Verification Engineer focuses on verifying and testing ASIC designs, whereas the New Grad Digital Design Engineer is involved in designing digital circuits. Both roles are essential in chip development but differ in their primary responsibilities and skill emphasis.

What are some common challenges new graduates face when starting as an ASIC design verification engineer, and how can they overcome them?

New grad ASIC Design Verification Engineers often encounter challenges such as understanding complex verification environments, learning industry-standard tools and methodologies like UVM, and effectively debugging hardware designs. To overcome these, it's helpful to actively seek mentorship from experienced team members, participate in code reviews, and utilize available documentation and training resources. Collaborating closely with designers and verification leads, asking questions, and consistently practicing hands-on simulations can accelerate learning and build confidence in tackling verification tasks.
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Senior Design Verification Engineer (BO - 01)

Cirrus Logic

Chandler, AZ • On-site

$133K - $163K/yr

Full-time

Re-posted 24 days ago

Job description

For over four decades, Cirrus Logic has been propelled by the top engineers in mixed-signal processing. Our rockstar team thrives on solving complex challenges with innovative end-user solutions for the world's top consumer brands. Cirrus Logic is also known for its award-winning culture, which was built on a foundation of inclusion and fairness, meaningful community engagement, and delivering enjoyable employee experiences at every turn. But we couldn't do it without our extraordinary workforce - and that's where you come in. Join our team and help us continue to make Cirrus Logic an exceptional place to grow your career!
Join our silicon design verification team and work closely with digital/analog designers, applications engineers, and manufacturing test, participating in all aspects of verification for complete mixed-signal IC developments of innovative solutions. You will work on complex verification systems and contribute to improvements in verification methodology while working alongside some of the most talented engineers in our industry.
Responsibilities:
  • Perform verification planning.
  • Testbench development using UVM methodologies.
  • Implement functional verification of mixed-signal ASICs.
  • Failure analysis and resolution, coverage analysis and population.
  • Digital/mixed-signal modeling.
  • Develop directed/constraint-random test generation, gate-simulations.
  • Regression debug support and other flow/infrastructure development.

Required Skills and Qualifications:
  • MS or PhD in Electrical Engineering or Computer Engineering.
  • Strong background with HDLs (e.g. Verilog, VHDL) and HVLs (e.g. SystemVerilog/UVM, OVM, AVM, Vera).
  • At least 5+ years of experience in silicon design or verification.

Preferred Skills and Qualifications:
  • Able to work closely with digital/analog designers, applications engineers, and manufacturing test to support both pre-silicon verification and post-silicon validation efforts.
  • Knowledge of signal processing and Verilog Assertions.
  • Ability to create, evaluate, debug, and improve verification processes.
  • Ability to mentor junior engineers in verification methodology.

#LI-Hybrid
#LI-EK1
Export control restrictions based upon applicable laws and regulations would prohibit candidates who are nationals of certain embargoed countries from working in this position without Cirrus Logic first obtaining an export license. Candidates for this role must be able to access technical data without a requirement for an export license. We are unable to sponsor or obtain export licenses for this role.
Cirrus Logic strives to select the best qualified applicant for any opening. Different approaches, ideas and points of view are both valued and respected. Employment decisions are made on the basis of job-related criteria without regard to race, color, religion, sex, national origin, age, protected veteran or disabled status, genetic information, or any other classification protected by applicable law.

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