Tucson, AZ · On-site
$105K - $145K/yr
... both directed test and constrained random methodologies. Design support is expected from ... to include the following: • FPGA/ASIC design (VHDL coding) or FPGA/ASIC verification ...
Tucson, AZ · On-site
$105K - $145K/yr
... both directed test and constrained random methodologies. Design support is expected from ... to include the following: • FPGA/ASIC design (VHDL coding) or FPGA/ASIC verification ...
Tucson, AZ · On-site
$128K/yr
... directed and constrained random tests, while tracking functional and code coverage * Demonstrate technical expertise in digital signal processing, FPGA/ASIC design/verification, CCA design ...
Tucson, AZ · On-site
$128K/yr
... directed and constrained random tests, while tracking functional and code coverage * Demonstrate technical expertise in digital signal processing, FPGA/ASIC design/verification, CCA design ...
Tucson, AZ · On-site
$114K - $157K/yr
... both directed test and constrained random methodologies. Design support is expected from ... to include the following: • FPGA/ASIC design (VHDL coding) or FPGA/ASIC verification ...
Tucson, AZ · On-site
$114K - $157K/yr
... both directed test and constrained random methodologies. Design support is expected from ... to include the following: • FPGA/ASIC design (VHDL coding) or FPGA/ASIC verification ...
Tucson, AZ · On-site
$128K/yr
... directed and constrained random tests, while tracking functional and code coverage * Demonstrate technical expertise in digital signal processing, FPGA/ASIC design/verification, CCA design ...
Tucson, AZ · On-site
$128K/yr
... directed and constrained random tests, while tracking functional and code coverage * Demonstrate technical expertise in digital signal processing, FPGA/ASIC design/verification, CCA design ...
... directed and constrained random tests, while tracking functional and code coverage * Demonstrate technical expertise in digital signal processing, FPGA/ASIC design/verification, CCA design ...
... directed and constrained random tests, while tracking functional and code coverage * Demonstrate technical expertise in digital signal processing, FPGA/ASIC design/verification, CCA design ...
... directed and constrained random tests, while tracking functional and code coverage * Demonstrate technical expertise in digital signal processing, FPGA/ASIC design/verification, CCA design ...
... directed and constrained random tests, while tracking functional and code coverage * Demonstrate technical expertise in digital signal processing, FPGA/ASIC design/verification, CCA design ...
Designs are verified against requirements using both directed test and constrained random ... FPGA/ASIC design (VHDL and/or Verilog coding) or FPGA/ASIC verification (SystemVerilog coding)
Designs are verified against requirements using both directed test and constrained random ... FPGA/ASIC design (VHDL and/or Verilog coding) or FPGA/ASIC verification (SystemVerilog coding)
Designs are verified against requirements using both directed test and constrained random ... FPGA/ASIC design (VHDL and/or Verilog coding) or FPGA/ASIC verification (SystemVerilog coding)
Designs are verified against requirements using both directed test and constrained random ... FPGA/ASIC design (VHDL and/or Verilog coding) or FPGA/ASIC verification (SystemVerilog coding)
Tucson, AZ · On-site
$116K - $160K/yr
Designs are verified against requirements using both directed test and constrained random ... FPGA/ASIC design (VHDL and/or Verilog coding) or FPGA/ASIC verification (SystemVerilog coding)
Tucson, AZ · On-site
$116K - $160K/yr
Designs are verified against requirements using both directed test and constrained random ... FPGA/ASIC design (VHDL and/or Verilog coding) or FPGA/ASIC verification (SystemVerilog coding)
Tucson, AZ · On-site
$116K - $160K/yr
Designs are verified against requirements using both directed test and constrained random ... FPGA/ASIC design (VHDL and/or Verilog coding) or FPGA/ASIC verification (SystemVerilog coding)
Tucson, AZ · On-site
$116K - $160K/yr
Designs are verified against requirements using both directed test and constrained random ... FPGA/ASIC design (VHDL and/or Verilog coding) or FPGA/ASIC verification (SystemVerilog coding)
Tucson, AZ · On-site
$116K - $149K/yr
... both directed test and constrained random methodologies. Design support is expected from ... to include the following: • FPGA/ASIC design (VHDL coding) or FPGA/ASIC verification ...
Tucson, AZ · On-site
$116K - $149K/yr
... both directed test and constrained random methodologies. Design support is expected from ... to include the following: • FPGA/ASIC design (VHDL coding) or FPGA/ASIC verification ...
Tucson, AZ · On-site
$122K - $157K/yr
... both directed test and constrained random methodologies. Design support is expected from ... to include the following: • FPGA/ASIC design (VHDL coding) or FPGA/ASIC verification ...
Tucson, AZ · On-site
$122K - $157K/yr
... both directed test and constrained random methodologies. Design support is expected from ... to include the following: • FPGA/ASIC design (VHDL coding) or FPGA/ASIC verification ...
Phoenix, AZ · On-site
Hands-on experience in Design Implementation and methodology (ASIC design, Fullchip Integration ... Direct customer engagement and technical leadership in advanced semiconductor design * Access to ...
Phoenix, AZ · On-site
Hands-on experience in Design Implementation and methodology (ASIC design, Fullchip Integration ... Direct customer engagement and technical leadership in advanced semiconductor design * Access to ...
Phoenix, AZ · On-site
Hands-on experience in Design Implementation and methodology (ASIC design, Fullchip Integration ... Direct customer engagement and technical leadership in advanced semiconductor design * Access to ...
Phoenix, AZ · On-site
Hands-on experience in Design Implementation and methodology (ASIC design, Fullchip Integration ... Direct customer engagement and technical leadership in advanced semiconductor design * Access to ...
Designs are verified against requirements using both directed test and constrained random ... FPGA/ASIC design (VHDL and/or Verilog coding) or FPGA/ASIC verification (SystemVerilog coding)
Designs are verified against requirements using both directed test and constrained random ... FPGA/ASIC design (VHDL and/or Verilog coding) or FPGA/ASIC verification (SystemVerilog coding)
Designs are verified against requirements using both directed test and constrained random ... FPGA/ASIC design (VHDL and/or Verilog coding) or FPGA/ASIC verification (SystemVerilog coding)
Designs are verified against requirements using both directed test and constrained random ... FPGA/ASIC design (VHDL and/or Verilog coding) or FPGA/ASIC verification (SystemVerilog coding)
Designs are verified against requirements using both directed test and constrained random ... FPGA/ASIC design (VHDL and/or Verilog coding) or FPGA/ASIC verification (SystemVerilog coding)
Designs are verified against requirements using both directed test and constrained random ... FPGA/ASIC design (VHDL and/or Verilog coding) or FPGA/ASIC verification (SystemVerilog coding)
Tucson, AZ · On-site
$98K - $132K/yr
Designs are verified against requirements using both directed test and constrained random ... FPGA/ASIC design (VHDL and/or Verilog coding) or FPGA/ASIC verification (SystemVerilog coding)
Tucson, AZ · On-site
$98K - $132K/yr
Designs are verified against requirements using both directed test and constrained random ... FPGA/ASIC design (VHDL and/or Verilog coding) or FPGA/ASIC verification (SystemVerilog coding)
Tucson, AZ · On-site
$116K - $160K/yr
Designs are verified against requirements using both directed test and constrained random ... FPGA/ASIC design experience in one or more of the following areas: * Radar processing techniques
Tucson, AZ · On-site
$116K - $160K/yr
Designs are verified against requirements using both directed test and constrained random ... FPGA/ASIC design experience in one or more of the following areas: * Radar processing techniques
Tucson, AZ · On-site
$116K - $160K/yr
Designs are verified against requirements using both directed test and constrained random ... FPGA/ASIC design experience in one or more of the following areas: * Radar processing techniques
Tucson, AZ · On-site
$116K - $160K/yr
Designs are verified against requirements using both directed test and constrained random ... FPGA/ASIC design experience in one or more of the following areas: * Radar processing techniques
The most popular types of Asic Design jobs in Arizona are:
For Director Asic Design jobs in Arizona, the most frequently searched job titles are:
The top searched job categories for Director Asic Design jobs in Arizona are:
Cities in Arizona with the most Director Asic Design job openings:
Tucson, AZ • On-site
$105K - $145K/yr
Other
Re-posted 16 days ago
