Tucson, AZ · On-site
$86.80 - $165.20/hr
Verify designs using self-checking techniques with directed and constrained random tests, while ... Experience with FPGA/ASIC design, including VHDL and/or Verilog coding or FPGA/ASIC verification ...
Tucson, AZ · On-site
$86.80 - $165.20/hr
Verify designs using self-checking techniques with directed and constrained random tests, while ... Experience with FPGA/ASIC design, including VHDL and/or Verilog coding or FPGA/ASIC verification ...
Tucson, AZ · On-site
$114K - $157K/yr
... both directed test and constrained random methodologies. Design support is expected from ... to include the following: • FPGA/ASIC design (VHDL coding) or FPGA/ASIC verification ...
Tucson, AZ · On-site
$114K - $157K/yr
... both directed test and constrained random methodologies. Design support is expected from ... to include the following: • FPGA/ASIC design (VHDL coding) or FPGA/ASIC verification ...
Tucson, AZ · On-site
$128K/yr
... directed and constrained random tests, while tracking functional and code coverage * Demonstrate technical expertise in digital signal processing, FPGA/ASIC design/verification, CCA design ...
Tucson, AZ · On-site
$128K/yr
... directed and constrained random tests, while tracking functional and code coverage * Demonstrate technical expertise in digital signal processing, FPGA/ASIC design/verification, CCA design ...
... directed and constrained random tests, while tracking functional and code coverage * Demonstrate technical expertise in digital signal processing, FPGA/ASIC design/verification, CCA design ...
... directed and constrained random tests, while tracking functional and code coverage * Demonstrate technical expertise in digital signal processing, FPGA/ASIC design/verification, CCA design ...
Tucson, AZ · On-site
$114K - $157K/yr
... both directed test and constrained random methodologies. Design support is expected from ... to include the following: • FPGA/ASIC design (VHDL coding) or FPGA/ASIC verification ...
Tucson, AZ · On-site
$114K - $157K/yr
... both directed test and constrained random methodologies. Design support is expected from ... to include the following: • FPGA/ASIC design (VHDL coding) or FPGA/ASIC verification ...
... directed and constrained random tests, while tracking functional and code coverage * Demonstrate technical expertise in digital signal processing, FPGA/ASIC design/verification, CCA design ...
... directed and constrained random tests, while tracking functional and code coverage * Demonstrate technical expertise in digital signal processing, FPGA/ASIC design/verification, CCA design ...
... directed and constrained random tests, while tracking functional and code coverage * Demonstrate technical expertise in digital signal processing, FPGA/ASIC design/verification, CCA design ...
... directed and constrained random tests, while tracking functional and code coverage * Demonstrate technical expertise in digital signal processing, FPGA/ASIC design/verification, CCA design ...
Designs are verified against requirements using both directed test and constrained random ... FPGA/ASIC design (VHDL and/or Verilog coding) or FPGA/ASIC verification (SystemVerilog coding)
Designs are verified against requirements using both directed test and constrained random ... FPGA/ASIC design (VHDL and/or Verilog coding) or FPGA/ASIC verification (SystemVerilog coding)
Designs are verified against requirements using both directed test and constrained random ... FPGA/ASIC design (VHDL and/or Verilog coding) or FPGA/ASIC verification (SystemVerilog coding)
Designs are verified against requirements using both directed test and constrained random ... FPGA/ASIC design (VHDL and/or Verilog coding) or FPGA/ASIC verification (SystemVerilog coding)
Designs are verified against requirements using both directed test and constrained random ... FPGA/ASIC design (VHDL and/or Verilog coding) or FPGA/ASIC verification (SystemVerilog coding)
Designs are verified against requirements using both directed test and constrained random ... FPGA/ASIC design (VHDL and/or Verilog coding) or FPGA/ASIC verification (SystemVerilog coding)
Tucson, AZ · On-site
$116K - $160K/yr
Designs are verified against requirements using both directed test and constrained random ... FPGA/ASIC design (VHDL and/or Verilog coding) or FPGA/ASIC verification (SystemVerilog coding)
Tucson, AZ · On-site
$116K - $160K/yr
Designs are verified against requirements using both directed test and constrained random ... FPGA/ASIC design (VHDL and/or Verilog coding) or FPGA/ASIC verification (SystemVerilog coding)
Chandler, AZ · On-site
$90 - $130/hr
Hands‑on experience in Design Implementation and methodology (ASIC design, full‑chip ... direct customer engagement and technical leadership; access to Intel's advanced foundry ...
Chandler, AZ · On-site
$90 - $130/hr
Hands‑on experience in Design Implementation and methodology (ASIC design, full‑chip ... direct customer engagement and technical leadership; access to Intel's advanced foundry ...
Tucson, AZ · On-site
$122K - $157K/yr
... both directed test and constrained random methodologies. Design support is expected from ... to include the following: • FPGA/ASIC design (VHDL coding) or FPGA/ASIC verification ...
Tucson, AZ · On-site
$122K - $157K/yr
... both directed test and constrained random methodologies. Design support is expected from ... to include the following: • FPGA/ASIC design (VHDL coding) or FPGA/ASIC verification ...
Tucson, AZ · On-site
$116K - $149K/yr
... both directed test and constrained random methodologies. Design support is expected from ... to include the following: • FPGA/ASIC design (VHDL coding) or FPGA/ASIC verification ...
Tucson, AZ · On-site
$116K - $149K/yr
... both directed test and constrained random methodologies. Design support is expected from ... to include the following: • FPGA/ASIC design (VHDL coding) or FPGA/ASIC verification ...
Phoenix, AZ · On-site
Hands-on experience in Design Implementation and methodology (ASIC design, Fullchip Integration ... Direct customer engagement and technical leadership in advanced semiconductor design * Access to ...
Phoenix, AZ · On-site
Hands-on experience in Design Implementation and methodology (ASIC design, Fullchip Integration ... Direct customer engagement and technical leadership in advanced semiconductor design * Access to ...
Phoenix, AZ · On-site
Hands-on experience in Design Implementation and methodology (ASIC design, Fullchip Integration ... Direct customer engagement and technical leadership in advanced semiconductor design * Access to ...
Phoenix, AZ · On-site
Hands-on experience in Design Implementation and methodology (ASIC design, Fullchip Integration ... Direct customer engagement and technical leadership in advanced semiconductor design * Access to ...
Designs are verified against requirements using both directed test and constrained random ... FPGA/ASIC design (VHDL and/or Verilog coding) or FPGA/ASIC verification (SystemVerilog coding)
Designs are verified against requirements using both directed test and constrained random ... FPGA/ASIC design (VHDL and/or Verilog coding) or FPGA/ASIC verification (SystemVerilog coding)
Designs are verified against requirements using both directed test and constrained random ... FPGA/ASIC design (VHDL and/or Verilog coding) or FPGA/ASIC verification (SystemVerilog coding)
Designs are verified against requirements using both directed test and constrained random ... FPGA/ASIC design (VHDL and/or Verilog coding) or FPGA/ASIC verification (SystemVerilog coding)
Designs are verified against requirements using both directed test and constrained random ... FPGA/ASIC design (VHDL and/or Verilog coding) or FPGA/ASIC verification (SystemVerilog coding)
Designs are verified against requirements using both directed test and constrained random ... FPGA/ASIC design (VHDL and/or Verilog coding) or FPGA/ASIC verification (SystemVerilog coding)
Tucson, AZ · On-site
$98K - $132K/yr
Designs are verified against requirements using both directed test and constrained random ... FPGA/ASIC design (VHDL and/or Verilog coding) or FPGA/ASIC verification (SystemVerilog coding)
Tucson, AZ · On-site
$98K - $132K/yr
Designs are verified against requirements using both directed test and constrained random ... FPGA/ASIC design (VHDL and/or Verilog coding) or FPGA/ASIC verification (SystemVerilog coding)
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Tucson, AZ • On-site
8.7
Based on 157 frontline employees who took The Breakroom Quiz
16th of 72 rated aerospace companies
People enjoy working here
Good employer
Recommended by students
Recommended by parents
Respectful managers
$86.80 - $165.20/hr
Other
Medical, Dental, Vision, Life, Retirement, PTO
Posted 20 days ago
Location: US-AZ-TUCSON-M02 - 1151 E Hermans Rd - BLDG M02; Onsite position.
Security Clearance RequirementsActive and transferable U.S. government-issued security clearance is required prior to start date. U.S. citizenship is required, as only U.S. citizens are eligible for a security clearance.
What You Will DoTypically requires a degree in Science, Technology, Engineering or Mathematics (STEM) and a minimum of 5 years of prior relevant experience.
Salary range: 86,800 USD – 165,200 USD.
Benefits include medical, dental, vision, life insurance, short-term disability, long-term disability, 401(k) match, flexible spending accounts, flexible work schedules, employee assistance program, Employee Scholar Program, parental leave, paid time off, and holidays. Incentive compensation programs are provided at the level of the position and may include short-term and long-term annual incentive compensation.
Equal Opportunity EmployerRTX is an Equal Opportunity Employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, age, disability or veteran status, or any other applicable state or federal protected class.
RTX provides affirmative action in employment for qualified individuals with a disability and protected veterans in compliance with Section 503 of the Rehabilitation Act and the Vietnam Era Veterans’ Readjustment Assistance Act.
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Pratt & Whitney has a long history of leadership and innovation in the field of aviation propulsion. Our story begins in the 1920s and has flourished throughout the decades. We have continuously transformed and reinvented our businesses to offer superior products and services to our customers. In 1925, the Pratt & Whitney Aircraft Company was founded by Frederick B. Rentschler, pioneer of the air-cooled radial engine design which enabled unprecedented power-to-weight ratio. Its first engine, the R-1340 Wasp engine, transformed military and commercial aviation and is still in use today. In 1928, the Canadian division of the Pratt & Whitney Aircraft Company was established. In 1944, Pratt & Whitney began its gas turbine and jet propulsion initiative. The company constructed a wind tunnel, laboratory and engineering center to support our allies’ efforts in World War II. In 1945, wartime production included more than 300,000 Pratt & Whitney engines, touted by service members as extremely dependable – a legacy that continues today. From there, Pratt & Whitney continued to design and innovate more powerful, agile, and reliable engines becoming a leader in the aerospace industry. Today, Pratt & Whitney has more than 85,000 engines in service and more than 16,000 customers worldwide.
Engineering professional services
10,000+ Employees
East Hartford, CT, US
1925
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