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Asic Design Manager Jobs in Arizona (NOW HIRING)

... management, design, test, and integration. The Section Leader will utilize advanced technical knowledge in FPGA/ASIC Design/Verification and/or Digital CCA Design, and an understand the impact of ...

... management, design, test, and integration. The Section Leader will utilize advanced technical knowledge in FPGA/ASIC Design/Verification and/or Digital CCA Design, and an understand the impact of ...

FPGA Engineer with Security Clearance

Tucson, AZ · On-site

$105K - $145K/yr

Design documentation and configuration management are required. Responsibilities to Anticipate: • ... to include the following: • FPGA/ASIC design (VHDL coding) or FPGA/ASIC verification ...

DFT Application Engineer

Chandler, AZ · On-site

$90 - $130/hr

Self‑driven and results‑oriented with ability to manage multiple complex tasks effectively ... Hands‑on experience in Design Implementation and methodology (ASIC design, full‑chip ...

FPGA Engineer

Tucson, AZ · On-site

$122K - $157K/yr

Design documentation and configuration management are required. Responsibilities to Anticipate: • ... to include the following: • FPGA/ASIC design (VHDL coding) or FPGA/ASIC verification ...

Self-driven and results-oriented with ability to manage multiple complex tasks effectively ... Hands-on experience in Design Implementation and methodology (ASIC design, Fullchip Integration ...

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Asic Design Manager information

See Arizona salary details

$39.1K

$106.7K

$187.8K

How much do asic design manager jobs pay per year?

As of Aug 28, 2026, the average yearly pay for asic design manager in Arizona is $106,693.00, according to ZipRecruiter salary data. Most workers in this role earn between $77,800.00 and $134,200.00 per year, depending on experience, location, and employer.

What does an ASIC Design Manager do?

An ASIC Design Manager oversees the design and development of Application Specific Integrated Circuits (ASICs), managing a team of engineers through the entire chip design process. They coordinate project timelines, ensure technical specifications are met, and facilitate communication between design, verification, and manufacturing teams. Their role also involves resource planning, risk management, and ensuring that the final product meets performance, cost, and quality targets.

What are the key skills and qualifications needed to thrive as an ASIC Design Manager?

To thrive as an ASIC Design Manager, you need expertise in digital and analog ASIC design, project management experience, and typically a degree in electrical engineering or a related field. Familiarity with industry-standard EDA tools (such as Cadence or Synopsys), verification methodologies, and knowledge of relevant design flows is crucial. Strong leadership, communication, and problem-solving skills help manage teams and coordinate with cross-functional stakeholders. These competencies ensure high-quality chip designs are delivered on time and meet performance and cost targets, which is vital for organizational success.

What are some common challenges faced by an ASIC Design Manager in leading multidisciplinary teams?

ASIC Design Managers often navigate the complexities of coordinating multidisciplinary teams, including digital, analog, verification, and physical design engineers. One common challenge is ensuring clear communication across these specialties to maintain alignment on project goals, timelines, and technical requirements. Additionally, managing shifting priorities, resolving technical bottlenecks, and balancing resource allocation are frequent hurdles. Successful managers foster collaboration, set clear expectations, and leverage structured project management practices to keep teams productive and motivated.

What is the difference between Asic Design Manager vs Asic Design Engineer?

AspectAsic Design ManagerAsic Design Engineer
ResponsibilitiesOversees ASIC design projects, manages teams, and coordinates with stakeholdersPerforms ASIC design, coding, simulation, and verification tasks
Required SkillsLeadership, project management, ASIC design knowledgeHardware description languages, circuit design, verification skills
ExperienceTypically 8+ years in ASIC design, with leadership experienceUsually 2-5 years in ASIC design roles
Work EnvironmentDesign teams, project planning, cross-functional collaborationDesign labs, simulation environments, coding and testing

The main difference between an Asic Design Manager and an Asic Design Engineer lies in their roles. The manager oversees projects and teams, focusing on leadership and coordination, while the engineer concentrates on technical ASIC design and implementation. Both roles require ASIC design expertise, but the manager's role is more strategic and supervisory.

What are the most commonly searched types of Asic Design jobs in Arizona?

The most popular types of Asic Design jobs in Arizona are:

What job categories do people searching Asic Design Manager jobs in Arizona look for?

The top searched job categories for Asic Design Manager jobs in Arizona are:

What cities in Arizona are hiring for Asic Design Manager jobs?

Cities in Arizona with the most Asic Design Manager job openings:

Infographic showing various Asic Design Manager job openings in Arizona as of August 2026, with employment types broken down into 87% Full Time, 10% Part Time, 2% Temporary, and 1% Contract. Highlights an 81% Physical, 2% Hybrid, and 17% Remote job distribution, with an average salary of $106,693 per year, or $51.3 per hour.

Senior Applications and Solutions Engineer - Foundry Services

Phoenix, AZ • On-site


Intel Corporation
Manufacturing • 10K+ employees

8.7

Company rating: 8.7 out of 10

Based on 147 frontline employees who took The Breakroom Quiz

18th of 159 rated electronics manufacturers

Great coworkers

People enjoy working here

Good employer


$122.44 - $232.19/hr

Other

Re-posted 23 days ago


Job description

Position Overview

We seek a Senior ASIC Design Engineer who will provide technical support to Intel Foundry Services customers on PDKs through ASIC design implementation flows and perform ASIC physical design execution focused on complex multi-voltage domain (UPF/CPF) designs and power-intent (VCLP and Conformal LP) verification signoff. This role drives quality improvements in design kits, supports customers through successful tape-outs, and performs ASIC design services on complex multi-voltage domain designs.

Key Responsibilities
  • Provide comprehensive technical support to Intel Foundry Services customers on PDKs, digital reference flows, and digital design signoff methodologies in multi-voltage domain implementation and verification.
  • Support and deliver ASIC/Digital tool/flow/methodology solutions, especially in multi-voltage domain design implementation and verification using Cadence and Synopsys tool suites.
  • Have deep knowledge of UPF/CPF (level-shifter, isolation, power gating, retention, always-on) implementation and verification using VCLP and Conformal LP; write and debug UPF/CPF for multi-voltage domain designs.
  • Drive customer success through expert guidance and hands-on experience in ASIC design execution.
  • Drive quality improvements in design kits and documentation through ASIC design reference flow validation and comprehensive documentation review.
  • Create application notes, technical design checklists, and deliver training presentations to customers and internal teams.
  • Establish and maintain high-quality design through implementation and verification methodologies and checklists.
Core Competencies
  • Self-driven and results-oriented with ability to manage multiple tasks effectively.
  • Strong teamwork skills to drive solutions for implementation challenges.
  • Excellent analytical problem-solving capabilities for complex design issues.
  • Effective communication skills with experience in collaboration and customer feedback.
Minimum Qualifications
  • US citizenship required.
  • Ability to obtain a US Government Security Clearance.
  • Bachelor’s degree in Electrical / Computer Engineering, Computer Science, or a STEM related field.
  • 4+ years of experience with advanced CMOS processes (16 nm and below).
  • 3+ years of experience in ASIC design implementation and verification in low power, multi-voltage domain.
  • 3+ years of experience in scripting languages such as Python, Perl, Tcl, and/or shell scripting.
Preferred Qualifications
  • Active US Government Security Clearance with at least Secret level.
  • Post-graduate degree in Electrical / Computer Engineering, Computer Science, or a STEM related field.
  • Experience with state-of-the-art process technology (7 nm and below).
  • Hands-on experience in physical design implementation and verification methodology for multi-voltage domain in SoC design.
  • Experience using EDA tools for multi-power domain design (UPF/CPF) implementation and power-intent verification (VCLP, Conformal LP) at block and SOC level.
  • Experience in writing and debugging UPF/CPF for multi-voltage domain designs.
  • Customer-facing experience in technical support roles.
Benefits and Work Arrangement
  • Annual salary range: $122,440.00 – $232,190.00 USD (US locations).
  • Hybrid work model allowing split between on-site and off-site work.
EEO Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

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Intel logo

About Intel

Sourced by ZipRecruiter

Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore's Law to bring smart, connected devices to every person on Earth

Industry

Manufacturing

Company size

10,000+ Employees

Headquarters location

Santa Clara, CA, US

Year founded

1968


What Intel employees say

Pay

Benefits

Hours and flexibility

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