Position Overview We seek a Senior ASIC Design Engineer to provide technical support to Intel ... Self-driven and results-oriented with ability to manage multiple tasks effectively * Strong ...
Position Overview We seek a Senior ASIC Design Engineer to provide technical support to Intel ... Self-driven and results-oriented with ability to manage multiple tasks effectively * Strong ...
Position Overview We seek a Senior ASIC Design Engineer to provide technical support to Intel ... Self-driven and results-oriented with ability to manage multiple tasks effectively * Strong ...
Position Overview We seek a Senior ASIC Design Engineer to provide technical support to Intel ... Self-driven and results-oriented with ability to manage multiple tasks effectively * Strong ...
FPGA VHDL Design Engineer US Citizenship required
$116K - $160K/yr
Knowledge and experience including: - Development of design documentation - Application of configuration management tools - Application of standard ASIC development design flows and methodologies for ...
FPGA VHDL Design Engineer US Citizenship required
$116K - $160K/yr
Knowledge and experience including: - Development of design documentation - Application of configuration management tools - Application of standard ASIC development design flows and methodologies for ...
FPGA VHDL Design Engineer US Citizenship required
Tucson, AZ · On-site
$116K - $160K/yr
Knowledge and experience including: - Development of design documentation - Application of configuration management tools - Application of standard ASIC development design flows and methodologies for ...
FPGA VHDL Design Engineer US Citizenship required
Tucson, AZ · On-site
$116K - $160K/yr
Knowledge and experience including: - Development of design documentation - Application of configuration management tools - Application of standard ASIC development design flows and methodologies for ...
Senior FPGA Design Engineer
$116K - $160K/yr
Design documentation and configuration management are required. What You Will Do * Design and ... FPGA/ASIC design, including VHDL and/or Verilog coding or FPGA/ASIC verification using ...
Senior FPGA Design Engineer
$116K - $160K/yr
Design documentation and configuration management are required. What You Will Do * Design and ... FPGA/ASIC design, including VHDL and/or Verilog coding or FPGA/ASIC verification using ...
Senior FPGA Design Engineer
$122K - $168K/yr
Design documentation and configuration management are required. What You Will Do * Design and ... FPGA/ASIC design, including VHDL and/or Verilog coding or FPGA/ASIC verification using ...
Senior FPGA Design Engineer
$122K - $168K/yr
Design documentation and configuration management are required. What You Will Do * Design and ... FPGA/ASIC design, including VHDL and/or Verilog coding or FPGA/ASIC verification using ...
Senior FPGA Design Engineer
Tucson, AZ · On-site
$116K - $160K/yr
Design documentation and configuration management are required. What You Will Do * Design and ... FPGA/ASIC design, including VHDL and/or Verilog coding or FPGA/ASIC verification using ...
Senior FPGA Design Engineer
Tucson, AZ · On-site
$116K - $160K/yr
Design documentation and configuration management are required. What You Will Do * Design and ... FPGA/ASIC design, including VHDL and/or Verilog coding or FPGA/ASIC verification using ...
Senior FPGA Design Engineer
$116K - $160K/yr
Design documentation and configuration management are required. What You Will Do * Design and ... FPGA/ASIC design, including VHDL and/or Verilog coding or FPGA/ASIC verification using ...
Senior FPGA Design Engineer
$116K - $160K/yr
Design documentation and configuration management are required. What You Will Do * Design and ... FPGA/ASIC design, including VHDL and/or Verilog coding or FPGA/ASIC verification using ...
Senior FPGA Design Engineer with Security Clearance
Tucson, AZ · On-site
$114K - $157K/yr
Design documentation and configuration management are required. What You Will Do * Design and ... FPGA/ASIC design, including VHDL and/or Verilog coding or FPGA/ASIC verification using ...
Senior FPGA Design Engineer with Security Clearance
Tucson, AZ · On-site
$114K - $157K/yr
Design documentation and configuration management are required. What You Will Do * Design and ... FPGA/ASIC design, including VHDL and/or Verilog coding or FPGA/ASIC verification using ...
FPGA Engineer with Security Clearance
Tucson, AZ · On-site
$105K - $145K/yr
Design documentation and configuration management are required. Responsibilities to Anticipate: • ... to include the following: • FPGA/ASIC design (VHDL coding) or FPGA/ASIC verification ...
New
FPGA Engineer with Security Clearance
Tucson, AZ · On-site
$105K - $145K/yr
Design documentation and configuration management are required. Responsibilities to Anticipate: • ... to include the following: • FPGA/ASIC design (VHDL coding) or FPGA/ASIC verification ...
New
FPGA Engineer with Security Clearance
Tucson, AZ · On-site
$114K - $157K/yr
Design documentation and configuration management are required. Responsibilities to Anticipate: • ... to include the following: • FPGA/ASIC design (VHDL coding) or FPGA/ASIC verification ...
FPGA Engineer with Security Clearance
Tucson, AZ · On-site
$114K - $157K/yr
Design documentation and configuration management are required. Responsibilities to Anticipate: • ... to include the following: • FPGA/ASIC design (VHDL coding) or FPGA/ASIC verification ...
Design documentation and configuration management are required. This position is 100% ONSITE in ... FPGA/ASIC design (VHDL and/or Verilog coding) or FPGA/ASIC verification (SystemVerilog coding)
Design documentation and configuration management are required. This position is 100% ONSITE in ... FPGA/ASIC design (VHDL and/or Verilog coding) or FPGA/ASIC verification (SystemVerilog coding)
Design documentation and configuration management are required. This position is 100% ONSITE in ... FPGA/ASIC design (VHDL and/or Verilog coding) or FPGA/ASIC verification (SystemVerilog coding)
Design documentation and configuration management are required. This position is 100% ONSITE in ... FPGA/ASIC design (VHDL and/or Verilog coding) or FPGA/ASIC verification (SystemVerilog coding)
Principal Electrical Engineer-FPGA Design- Onsite Tucson, AZ
Tucson, AZ · On-site
$116K - $160K/yr
Design documentation and configuration management are required. This position is 100% ONSITE in ... FPGA/ASIC design (VHDL and/or Verilog coding) or FPGA/ASIC verification (SystemVerilog coding)
Principal Electrical Engineer-FPGA Design- Onsite Tucson, AZ
Tucson, AZ · On-site
$116K - $160K/yr
Design documentation and configuration management are required. This position is 100% ONSITE in ... FPGA/ASIC design (VHDL and/or Verilog coding) or FPGA/ASIC verification (SystemVerilog coding)
Design documentation and configuration management are required. This position is 100% ONSITE in ... FPGA/ASIC design (VHDL and/or Verilog coding) or FPGA/ASIC verification (SystemVerilog coding)
Design documentation and configuration management are required. This position is 100% ONSITE in ... FPGA/ASIC design (VHDL and/or Verilog coding) or FPGA/ASIC verification (SystemVerilog coding)
Principal Electrical Engineer-FPGA Design- Onsite Tucson, AZ with Security Clearance
Tucson, AZ · On-site
$114K - $157K/yr
Design documentation and configuration management are required. This position is 100% ONSITE in ... FPGA/ASIC design (VHDL and/or Verilog coding) or FPGA/ASIC verification (SystemVerilog coding)
Principal Electrical Engineer-FPGA Design- Onsite Tucson, AZ with Security Clearance
Tucson, AZ · On-site
$114K - $157K/yr
Design documentation and configuration management are required. This position is 100% ONSITE in ... FPGA/ASIC design (VHDL and/or Verilog coding) or FPGA/ASIC verification (SystemVerilog coding)
FPGA Embedded Engineer with Security Clearance
Tucson, AZ · On-site
$116K - $149K/yr
Design documentation and configuration management are required. Responsibilities to Anticipate: • ... to include the following: • FPGA/ASIC design (VHDL coding) or FPGA/ASIC verification ...
FPGA Embedded Engineer with Security Clearance
Tucson, AZ · On-site
$116K - $149K/yr
Design documentation and configuration management are required. Responsibilities to Anticipate: • ... to include the following: • FPGA/ASIC design (VHDL coding) or FPGA/ASIC verification ...
FPGA Engineer
Tucson, AZ · On-site
$122K - $157K/yr
Design documentation and configuration management are required. Responsibilities to Anticipate: • ... to include the following: • FPGA/ASIC design (VHDL coding) or FPGA/ASIC verification ...
FPGA Engineer
Tucson, AZ · On-site
$122K - $157K/yr
Design documentation and configuration management are required. Responsibilities to Anticipate: • ... to include the following: • FPGA/ASIC design (VHDL coding) or FPGA/ASIC verification ...
Self-driven and results-oriented with ability to manage multiple complex tasks effectively ... Hands-on experience in Design Implementation and methodology (ASIC design, Fullchip Integration ...
Self-driven and results-oriented with ability to manage multiple complex tasks effectively ... Hands-on experience in Design Implementation and methodology (ASIC design, Fullchip Integration ...
DFT Application Engineer
Phoenix, AZ · On-site
Self-driven and results-oriented with ability to manage multiple complex tasks effectively ... Hands-on experience in Design Implementation and methodology (ASIC design, Fullchip Integration ...
DFT Application Engineer
Phoenix, AZ · On-site
Self-driven and results-oriented with ability to manage multiple complex tasks effectively ... Hands-on experience in Design Implementation and methodology (ASIC design, Fullchip Integration ...
Asic Design Manager information
See Arizona salary details
$39.1K - $52.7K
4% of jobs
$52.7K - $66.2K
8% of jobs
$76.1K is the 25th percentile. Wages below this are outliers.
$66.2K - $79.7K
17% of jobs
The median wage is $92.2K / yr.
$79.7K - $93.2K
22% of jobs
$93.2K - $106.7K
15% of jobs
$106.7K - $120.2K
6% of jobs
$124.6K is the 75th percentile. Wages above this are outliers.
$120.2K - $133.7K
7% of jobs
$133.7K - $147.2K
7% of jobs
$147.2K - $160.8K
8% of jobs
$160.8K - $174.3K
2% of jobs
$174.3K - $187.8K
2% of jobs
$39.1K
$106.7K
$187.8K
How much do asic design manager jobs pay per year?
As of Jul 19, 2026, the average yearly pay for asic design manager in Arizona is $106,693.00, according to ZipRecruiter salary data. Most workers in this role earn between $77,800.00 and $134,200.00 per year, depending on experience, location, and employer.
What is the difference between Asic Design Manager vs Asic Design Engineer?
| Aspect | Asic Design Manager | Asic Design Engineer |
|---|---|---|
| Responsibilities | Oversees ASIC design projects, manages teams, and coordinates with stakeholders | Performs ASIC design, coding, simulation, and verification tasks |
| Required Skills | Leadership, project management, ASIC design knowledge | Hardware description languages, circuit design, verification skills |
| Experience | Typically 8+ years in ASIC design, with leadership experience | Usually 2-5 years in ASIC design roles |
| Work Environment | Design teams, project planning, cross-functional collaboration | Design labs, simulation environments, coding and testing |
The main difference between an Asic Design Manager and an Asic Design Engineer lies in their roles. The manager oversees projects and teams, focusing on leadership and coordination, while the engineer concentrates on technical ASIC design and implementation. Both roles require ASIC design expertise, but the manager's role is more strategic and supervisory.
What are the key skills and qualifications needed to thrive as an ASIC Design Manager, and why are they important?
To thrive as an ASIC Design Manager, you need expertise in digital and analog ASIC design, project management experience, and typically a degree in electrical engineering or a related field. Familiarity with industry-standard EDA tools (such as Cadence or Synopsys), verification methodologies, and knowledge of relevant design flows is crucial. Strong leadership, communication, and problem-solving skills help manage teams and coordinate with cross-functional stakeholders. These competencies ensure high-quality chip designs are delivered on time and meet performance and cost targets, which is vital for organizational success.
What are some common challenges faced by an ASIC Design Manager in leading multidisciplinary teams?
ASIC Design Managers often navigate the complexities of coordinating multidisciplinary teams, including digital, analog, verification, and physical design engineers. One common challenge is ensuring clear communication across these specialties to maintain alignment on project goals, timelines, and technical requirements. Additionally, managing shifting priorities, resolving technical bottlenecks, and balancing resource allocation are frequent hurdles. Successful managers foster collaboration, set clear expectations, and leverage structured project management practices to keep teams productive and motivated.
What does an ASIC Design Manager do?
An ASIC Design Manager oversees the design and development of Application Specific Integrated Circuits (ASICs), managing a team of engineers through the entire chip design process. They coordinate project timelines, ensure technical specifications are met, and facilitate communication between design, verification, and manufacturing teams. Their role also involves resource planning, risk management, and ensuring that the final product meets performance, cost, and quality targets.
What are the most commonly searched types of Asic Design jobs in Arizona? The most popular types of Asic Design jobs in Arizona are:
What are popular job titles related to Asic Design Manager jobs in Arizona? For Asic Design Manager jobs in Arizona, the most frequently searched job titles are:
What job categories do people searching Asic Design Manager jobs in Arizona look for? The top searched job categories for Asic Design Manager jobs in Arizona are:
What cities in Arizona are hiring for Asic Design Manager jobs? Cities in Arizona with the most Asic Design Manager job openings:
Full-time
Medical, Retirement, PTO
Re-posted 13 days ago
Intel rating
8.7
Based on 147 frontline employees who took The Breakroom Quiz
11th of 143 rated electronics manufacturers
Job description
Job Details:Job Description:
Intel Foundry is a systems foundry transforming the global semiconductor industry by delivering cutting-edge silicon process and packaging technology leadership for the AI era. Intel Foundry will be differentiated from other foundries by our world class industry-leading IP portfolio that customers can choose from including rich IP ecosystem including x86 cores, graphics, AI, and Arm/RISC-V IPs, world-class design services, and operationally resilient global manufacturing with committed capacity in the US and Europe.
Position Overview
We seek a Senior ASIC Design Engineer to provide technical support to Intel Foundry Services customers on PDKs through ASIC design implementation flows and to perform ASIC physical design execution with specialized focus on complex multi-voltage domain (UPF/CPF) designs and power-intent (VCLP and Conformal LP) verification signoff. This role drives quality improvements in design kits, supports customers through successful tape-outs, and performs ASIC design service on complex multi-voltage domain designs.
Key Responsibilities
Customer Technical Support and ASIC Design Execution
- Provide comprehensive technical support to Intel Foundry Services customers on PDKs, digital reference flows and digital design signoff methodologies in multi-voltage domain implementation and verification.
- Support and deliver ASIC/Digital tool/flow/methodology solutions, especially in multi-voltage domain design implementation and verification using Cadence and Synopsys tool suites. Have deep knowledge of UPF/CPF (level-shifter, isolation, power gating, retention, always-on) implementation and verification using (VCLP and Conformal LP). Have experience in writing and debugging UPF/CPF for multi-voltage domain designs.
- Drive customer success through expert guidance and have strong hand-on experience in ASIC design execution
Quality Assurance and Documentation
- Drive quality improvements in design kits and documentation through ASIC design reference flow validation and comprehensive documentation review
- Create application notes, technical design checklists, and deliver training presentations to customers and internal teams
- Establish and maintain high quality design through implementation and verification methodologies and checklists
Core Competencies
- Self-driven and results-oriented with ability to manage multiple tasks effectively
- Strong teamwork skills to drive solutions for implementation challenge
- Analytical problem-solving capabilities for complex design issues
- Excellent communication skills with experience in collaboration and customer feedback
The Minimum qualifications are required to be considered for this position. Minimum qualifications listed below would be obtained through a combination of industry relevant job experience, internship experience and / or schoolwork/classes/research. The preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
Minimum Qualifications
- US Citizenship required.
- Ability to obtain a US Government Security Clearance.
- Bachelor's degree in Electrical / Computer Engineering, Computer Science, or in a STEM related field of study.
- 4+ years of experience with advanced CMOS processes (16nm and below).
- 3+ years of experience in ASIC design implementing and verification in area of low power, multi-voltage domain
- 3+ years of experience in scripting languages like Python, Perl, Tcl, and/or shell scripting
Preferred Qualifications
- Active US Government Security Clearance with a minimum of Secret level
- Post Graduate degree in Electrical / Computer Engineering, Computer Science, or in a STEM related field of study
- Experience with state-of-the-art process technology (7nm and below)
- Hands-on experience in physical design Implementation and verification methodology for multi-voltage domain in SoC design
- Experience using EDA tools for multi-power domain design (UPF/CPF) implementation and power-intent verification (VCLP, Conformal LP) at block and at SOC level
- Experience in writing and debugging UPF/CPF for multi-voltage domain designs
- Customer-facing experience in technical support roles
# cj
Job Type:Experienced HireShift:Shift 1 (United States of America)Primary Location: US, Arizona, PhoenixAdditional Locations:US, California, Santa Clara, US, Oregon, HillsboroBusiness group:The Central Engineering Group (CEG) is Intel's data-driven organization that builds scalable engineering solutions across three pillars: Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom silicon), and Foundry Enablement (supporting top customers and validating technologies). The team focuses on customer-driven, end-to-end solutions with short development cycles to deliver measurable business impact across Intel's product and foundry businesses.Posting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of TrustN/ABenefitsWe offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.
Annual Salary Range for jobs which could be performed in the US: $122,440.00-232,190.00 USDThe range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.*
ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.
About Intel
Sourced by ZipRecruiter
Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore's Law to bring smart, connected devices to every person on Earth
Industry
Manufacturing
Company size
10,000+ Employees
Headquarters location
Santa Clara, CA, US
Year founded
1968