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Senior Asic Design Engineer Jobs in Arizona (NOW HIRING)

Senior FPGA Design Engineer

Phoenix, AZ

$122K - $168K/yr

As a Senior FPGA Design Engineer you will develop FPGA designs for all major vendors and device ... FPGA/ASIC design, including VHDL and/or Verilog coding or FPGA/ASIC verification using ...

Senior FPGA Design Engineer

Tucson, AZ

$116K - $160K/yr

As a Senior FPGA Design Engineer you will develop FPGA designs for all major vendors and device ... FPGA/ASIC design, including VHDL and/or Verilog coding or FPGA/ASIC verification using ...

Senior FPGA Design Engineer

Tucson, AZ

$116K - $160K/yr

As a Senior FPGA Design Engineer you will develop FPGA designs for all major vendors and device ... FPGA/ASIC design, including VHDL and/or Verilog coding or FPGA/ASIC verification using ...

Senior FPGA Design Engineer

Tucson, AZ · On-site

$86.80 - $165.20/hr

Lead small teams and mentor junior engineers. * Support internal and external technical reviews ... Experience with FPGA/ASIC design, including VHDL and/or Verilog coding or FPGA/ASIC verification ...

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Senior Asic Design Engineer information

See Arizona salary details

$130.5K

$165.6K

$204.5K

How much do senior asic design engineer jobs pay per year?

As of Aug 13, 2026, the average yearly pay for senior asic design engineer in Arizona is $165,553.00, according to ZipRecruiter salary data. Most workers in this role earn between $148,200.00 and $181,700.00 per year, depending on experience, location, and employer.

What does a senior ASIC design engineer do?

A Senior ASIC Design Engineer is responsible for designing and developing Application-Specific Integrated Circuits (ASICs) used in a wide range of electronic devices. They lead the architecture, implementation, and verification of complex digital or mixed-signal circuits, often collaborating with cross-functional teams. This senior role involves optimizing designs for performance, power, and area while ensuring that the final product meets stringent technical and quality requirements. Additionally, they may mentor junior engineers and contribute to design methodologies and best practices within the organization.

What are the key skills and qualifications needed to thrive as a senior ASIC design engineer?

To thrive as a Senior ASIC Design Engineer, you need deep expertise in digital and/or analog circuit design, strong knowledge of hardware description languages (HDLs) like Verilog or VHDL, and a relevant engineering degree. Familiarity with EDA tools such as Synopsys, Cadence, and Mentor Graphics, as well as experience with simulation, synthesis, and verification methodologies, is typically required. Outstanding problem-solving, collaboration, and communication skills set top performers apart in this role. These competencies ensure efficient design cycles, robust chip functionality, and successful delivery of complex semiconductor projects.

What is the difference between Senior Asic Design Engineer vs Digital IC Design Engineer?

AspectSenior Asic Design EngineerDigital IC Design Engineer
Required CredentialsBachelor's/Master's in Electrical Engineering, VLSI, or related fields; experience in ASIC designBachelor's/Master's in Electrical Engineering, VLSI, or related fields; focus on digital circuit design
Work EnvironmentDesign teams in semiconductor or tech companies, hardware development labsIntegrated circuit design teams, research labs, semiconductor companies
Employer & Industry UsageUsed in ASIC development, FPGA design, hardware accelerationUsed in digital chip design, FPGA development, digital system integration

The main difference is that a Senior Asic Design Engineer specializes in designing application-specific integrated circuits, often leading complex projects, while a Digital IC Design Engineer focuses on digital circuit design within integrated circuits. Both roles require similar educational backgrounds and work environments but differ in project scope and specialization.

What are some common challenges senior ASIC design engineers face when collaborating with cross-functional teams?

Senior ASIC Design Engineers often work closely with verification, software, and systems teams throughout the development cycle. One common challenge is ensuring clear communication of design specifications and changes, as misunderstandings can lead to integration issues or delays. Balancing multiple project timelines and adapting to evolving requirements from other departments can also be demanding. Building strong, collaborative relationships and using robust documentation and project management tools are key to overcoming these challenges.
What are the most commonly searched types of Asic Design Engineer jobs in Arizona? The most popular types of Asic Design Engineer jobs in Arizona are:
What are popular job titles related to Senior Asic Design Engineer jobs in Arizona? For Senior Asic Design Engineer jobs in Arizona, the most frequently searched job titles are:
What job categories do people searching Senior Asic Design Engineer jobs in Arizona look for? The top searched job categories for Senior Asic Design Engineer jobs in Arizona are:
What are popular job titles related to Senior Asic Design Engineer jobs in AZ? For Senior Asic Design Engineer jobs in AZ, the most frequently searched job titles are:
Infographic showing various Senior Asic Design Engineer job openings in Arizona as of August 2026, with employment types broken down into 1% Internship, 88% Full Time, 7% Part Time, and 4% Contract. Highlights an 84% Physical, 5% Hybrid, and 11% Remote job distribution, with an average salary of $165,553 per year, or $79.6 per hour.

Senior Applications and Solutions Engineer - Foundry Services

Intel Corporation

Phoenix, AZ • On-site

$122.44 - $232.19/hr

Other

Re-posted 8 days ago


Intel rating

8.7

Company rating: 8.7 out of 10

Based on 147 frontline employees who took The Breakroom Quiz

19th of 157 rated electronics manufacturers


Job description

Position Overview

We seek a Senior ASIC Design Engineer who will provide technical support to Intel Foundry Services customers on PDKs through ASIC design implementation flows and perform ASIC physical design execution focused on complex multi-voltage domain (UPF/CPF) designs and power-intent (VCLP and Conformal LP) verification signoff. This role drives quality improvements in design kits, supports customers through successful tape-outs, and performs ASIC design services on complex multi-voltage domain designs.

Key Responsibilities
  • Provide comprehensive technical support to Intel Foundry Services customers on PDKs, digital reference flows, and digital design signoff methodologies in multi-voltage domain implementation and verification.
  • Support and deliver ASIC/Digital tool/flow/methodology solutions, especially in multi-voltage domain design implementation and verification using Cadence and Synopsys tool suites.
  • Have deep knowledge of UPF/CPF (level-shifter, isolation, power gating, retention, always-on) implementation and verification using VCLP and Conformal LP; write and debug UPF/CPF for multi-voltage domain designs.
  • Drive customer success through expert guidance and hands-on experience in ASIC design execution.
  • Drive quality improvements in design kits and documentation through ASIC design reference flow validation and comprehensive documentation review.
  • Create application notes, technical design checklists, and deliver training presentations to customers and internal teams.
  • Establish and maintain high-quality design through implementation and verification methodologies and checklists.
Core Competencies
  • Self-driven and results-oriented with ability to manage multiple tasks effectively.
  • Strong teamwork skills to drive solutions for implementation challenges.
  • Excellent analytical problem-solving capabilities for complex design issues.
  • Effective communication skills with experience in collaboration and customer feedback.
Minimum Qualifications
  • US citizenship required.
  • Ability to obtain a US Government Security Clearance.
  • Bachelor’s degree in Electrical / Computer Engineering, Computer Science, or a STEM related field.
  • 4+ years of experience with advanced CMOS processes (16 nm and below).
  • 3+ years of experience in ASIC design implementation and verification in low power, multi-voltage domain.
  • 3+ years of experience in scripting languages such as Python, Perl, Tcl, and/or shell scripting.
Preferred Qualifications
  • Active US Government Security Clearance with at least Secret level.
  • Post-graduate degree in Electrical / Computer Engineering, Computer Science, or a STEM related field.
  • Experience with state-of-the-art process technology (7 nm and below).
  • Hands-on experience in physical design implementation and verification methodology for multi-voltage domain in SoC design.
  • Experience using EDA tools for multi-power domain design (UPF/CPF) implementation and power-intent verification (VCLP, Conformal LP) at block and SOC level.
  • Experience in writing and debugging UPF/CPF for multi-voltage domain designs.
  • Customer-facing experience in technical support roles.
Benefits and Work Arrangement
  • Annual salary range: $122,440.00 – $232,190.00 USD (US locations).
  • Hybrid work model allowing split between on-site and off-site work.
EEO Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

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About Intel

Sourced by ZipRecruiter

Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore's Law to bring smart, connected devices to every person on Earth

Industry

Manufacturing

Company size

10,000+ Employees

Headquarters location

Santa Clara, CA, US

Year founded

1968