Position Overview We seek a Senior ASIC Design Engineer to provide technical support to Intel Foundry Services customers on PDKs through ASIC design implementation flows and to perform ASIC physical ...
Position Overview We seek a Senior ASIC Design Engineer to provide technical support to Intel Foundry Services customers on PDKs through ASIC design implementation flows and to perform ASIC physical ...
Position Overview We seek a Senior ASIC Design Engineer to provide technical support to Intel Foundry Services customers on PDKs through ASIC design implementation flows and to perform ASIC physical ...
Position Overview We seek a Senior ASIC Design Engineer to provide technical support to Intel Foundry Services customers on PDKs through ASIC design implementation flows and to perform ASIC physical ...
Sr Advanced ASIC FPGA Engineer
Scottsdale, AZ · On-site
$152.46K - $169.14K/yr
Responsibilities for this Position Duties and Tasks: • Responsible for definition, design ... ASIC (Application Specific Integrated Circuit) and/or FPGA (Field Programmable Gate Array ...
Sr Advanced ASIC FPGA Engineer
Scottsdale, AZ · On-site
$152.46K - $169.14K/yr
Responsibilities for this Position Duties and Tasks: • Responsible for definition, design ... ASIC (Application Specific Integrated Circuit) and/or FPGA (Field Programmable Gate Array ...
Sr Advanced ASIC FPGA Engineer
Scottsdale, AZ · Hybrid
$152.46K - $169.14K/yr
Duties and Tasks: • Responsible for definition, design, verification and documentation for ASIC (Application Specific Integrated Circuit) and/or FPGA (Field Programmable Gate Array) developments ...
Sr Advanced ASIC FPGA Engineer
Scottsdale, AZ · Hybrid
$152.46K - $169.14K/yr
Duties and Tasks: • Responsible for definition, design, verification and documentation for ASIC (Application Specific Integrated Circuit) and/or FPGA (Field Programmable Gate Array) developments ...
Position Overview We seek a Senior Applications and Solutions Engineer to provide technical support ... Support and deliver ASIC/Digital tool/flow/methodology solutions using Cadence tool suites to ...
Position Overview We seek a Senior Applications and Solutions Engineer to provide technical support ... Support and deliver ASIC/Digital tool/flow/methodology solutions using Cadence tool suites to ...
Senior FPGA Design Engineer
$116.30K - $160.30K/yr
As a Senior FPGA Design Engineer you will develop FPGA designs for all major vendors and device ... FPGA/ASIC design, including VHDL and/or Verilog coding or FPGA/ASIC verification using ...
Senior FPGA Design Engineer
$116.30K - $160.30K/yr
As a Senior FPGA Design Engineer you will develop FPGA designs for all major vendors and device ... FPGA/ASIC design, including VHDL and/or Verilog coding or FPGA/ASIC verification using ...
Senior FPGA Design Engineer
Tucson, AZ · On-site
$116.30K - $160.30K/yr
As a Senior FPGA Design Engineer you will develop FPGA designs for all major vendors and device ... FPGA/ASIC design, including VHDL and/or Verilog coding or FPGA/ASIC verification using ...
Senior FPGA Design Engineer
Tucson, AZ · On-site
$116.30K - $160.30K/yr
As a Senior FPGA Design Engineer you will develop FPGA designs for all major vendors and device ... FPGA/ASIC design, including VHDL and/or Verilog coding or FPGA/ASIC verification using ...
Senior FPGA Design Engineer
$122.10K - $168.30K/yr
As a Senior FPGA Design Engineer you will develop FPGA designs for all major vendors and device ... FPGA/ASIC design, including VHDL and/or Verilog coding or FPGA/ASIC verification using ...
Senior FPGA Design Engineer
$122.10K - $168.30K/yr
As a Senior FPGA Design Engineer you will develop FPGA designs for all major vendors and device ... FPGA/ASIC design, including VHDL and/or Verilog coding or FPGA/ASIC verification using ...
Senior FPGA Design Engineer
Tucson, AZ · On-site
$116.30K - $160.30K/yr
As a Senior FPGA Design Engineer you will develop FPGA designs for all major vendors and device ... FPGA/ASIC design, including VHDL and/or Verilog coding or FPGA/ASIC verification using ...
Senior FPGA Design Engineer
Tucson, AZ · On-site
$116.30K - $160.30K/yr
As a Senior FPGA Design Engineer you will develop FPGA designs for all major vendors and device ... FPGA/ASIC design, including VHDL and/or Verilog coding or FPGA/ASIC verification using ...
Support and deliver ASIC/Digital tool/flow/methodologysolutions using Cadence tool suites to ... Drive quality improvements in design kits and documentation through ASIC design reference flow ...
Support and deliver ASIC/Digital tool/flow/methodologysolutions using Cadence tool suites to ... Drive quality improvements in design kits and documentation through ASIC design reference flow ...
This Hardware Engineering position is located in San Jose, CA, and is open to remote applicants ... Design, document, and develop ASIC packages for high-volume, high-quality release, including post ...
This Hardware Engineering position is located in San Jose, CA, and is open to remote applicants ... Design, document, and develop ASIC packages for high-volume, high-quality release, including post ...
FPGA VHDL Design Engineer US Citizenship required
$116.30K - $160.30K/yr
Our network consists of both subject matter experts in a wide variety of technical areas and senior ... We have a PERM position in sunny Tucson, AZ for an ASIC FPGA Designer. There are several positions ...
FPGA VHDL Design Engineer US Citizenship required
$116.30K - $160.30K/yr
Our network consists of both subject matter experts in a wide variety of technical areas and senior ... We have a PERM position in sunny Tucson, AZ for an ASIC FPGA Designer. There are several positions ...
As a Principal Digital Design Engineer, the candidate shall be working with multi-sited global ... Experience in ASIC design flow including lint checking, Crossing Clock domain checking, DFT ...
As a Principal Digital Design Engineer, the candidate shall be working with multi-sited global ... Experience in ASIC design flow including lint checking, Crossing Clock domain checking, DFT ...
As a Principal Digital Design Engineer, the candidate shall be working with multi-sited global ... Experience in ASIC design flow including lint checking, Crossing Clock domain checking, DFT ...
As a Principal Digital Design Engineer, the candidate shall be working with multi-sited global ... Experience in ASIC design flow including lint checking, Crossing Clock domain checking, DFT ...
FPGA VHDL Design Engineer US Citizenship required
Tucson, AZ · On-site
$116.30K - $160.30K/yr
Our network consists of both subject matter experts in a wide variety of technical areas and senior ... We have a PERM position in sunny Tucson, AZ for an ASIC FPGA Designer. There are several positions ...
FPGA VHDL Design Engineer US Citizenship required
Tucson, AZ · On-site
$116.30K - $160.30K/yr
Our network consists of both subject matter experts in a wide variety of technical areas and senior ... We have a PERM position in sunny Tucson, AZ for an ASIC FPGA Designer. There are several positions ...
Advanced ASIC FPGA Engineer
Scottsdale, AZ · On-site
$122.79K - $136.22K/yr
Responsibilities for this Position Duties and Tasks: • Responsible for definition, design ... with senior levels of internal work groups • Works under limited direction • Contact with ...
Advanced ASIC FPGA Engineer
Scottsdale, AZ · On-site
$122.79K - $136.22K/yr
Responsibilities for this Position Duties and Tasks: • Responsible for definition, design ... with senior levels of internal work groups • Works under limited direction • Contact with ...
Advanced ASIC FPGA Engineer
Scottsdale, AZ · On-site
$119.60K - $164.80K/yr
Duties and Tasks: • Responsible for definition, design, verification and documentation for ASIC ... with senior levels of internal work groups • Works under limited direction • Contact with ...
Advanced ASIC FPGA Engineer
Scottsdale, AZ · On-site
$119.60K - $164.80K/yr
Duties and Tasks: • Responsible for definition, design, verification and documentation for ASIC ... with senior levels of internal work groups • Works under limited direction • Contact with ...
As a Senior Principal FPGA Design Engineer you will develop FPGA designs for all major vendors and ... FPGA/ASIC design (VHDL and/or Verilog coding) or FPGA/ASIC verification (SystemVerilog coding)
As a Senior Principal FPGA Design Engineer you will develop FPGA designs for all major vendors and ... FPGA/ASIC design (VHDL and/or Verilog coding) or FPGA/ASIC verification (SystemVerilog coding)
Senior Principal Electrical Engineer-FPGA Design- Onsite Tucson, AZ
$98.30K - $132.40K/yr
As a Senior Principal FPGA Design Engineer you will develop FPGA designs for all major vendors and ... FPGA/ASIC design (VHDL and/or Verilog coding) or FPGA/ASIC verification (SystemVerilog coding)
Senior Principal Electrical Engineer-FPGA Design- Onsite Tucson, AZ
$98.30K - $132.40K/yr
As a Senior Principal FPGA Design Engineer you will develop FPGA designs for all major vendors and ... FPGA/ASIC design (VHDL and/or Verilog coding) or FPGA/ASIC verification (SystemVerilog coding)
Senior FPGA Design Engineer
Chandler, AZ · On-site
$101.10K - $136.10K/yr
Senior FPGA Engineer III Department: Engineering->Platforms->FPGA SoC Group Reports To: Director ... Strong digital design engineer with FPGA/ASIC SoC design experience * Strong FPGA Implementation ...
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Senior FPGA Design Engineer
Chandler, AZ · On-site
$101.10K - $136.10K/yr
Senior FPGA Engineer III Department: Engineering->Platforms->FPGA SoC Group Reports To: Director ... Strong digital design engineer with FPGA/ASIC SoC design experience * Strong FPGA Implementation ...
Senior Asic Design Engineer information
See Arizona salary details
$130.5K - $137.2K
4% of jobs
$137.2K - $143.9K
12% of jobs
$147.9K is the 25th percentile. Wages below this are outliers.
$143.9K - $150.7K
16% of jobs
$150.7K - $157.4K
16% of jobs
The median wage is $158.8K / yr.
$157.4K - $164.1K
13% of jobs
$164.1K - $170.9K
8% of jobs
$176.9K is the 75th percentile. Wages above this are outliers.
$170.9K - $177.6K
7% of jobs
$177.6K - $184.3K
6% of jobs
$184.3K - $191.1K
7% of jobs
$191.1K - $197.8K
5% of jobs
$197.8K - $204.5K
5% of jobs
$130.5K
$165.6K
$204.5K
How much do senior asic design engineer jobs pay per year?
As of May 28, 2026, the average yearly pay for senior asic design engineer in Arizona is $165,553.00, according to ZipRecruiter salary data. Most workers in this role earn between $148,200.00 and $181,700.00 per year, depending on experience, location, and employer.
What are the key skills and qualifications needed to thrive as a Senior ASIC Design Engineer, and why are they important?
To thrive as a Senior ASIC Design Engineer, you need deep expertise in digital and/or analog circuit design, strong knowledge of hardware description languages (HDLs) like Verilog or VHDL, and a relevant engineering degree. Familiarity with EDA tools such as Synopsys, Cadence, and Mentor Graphics, as well as experience with simulation, synthesis, and verification methodologies, is typically required. Outstanding problem-solving, collaboration, and communication skills set top performers apart in this role. These competencies ensure efficient design cycles, robust chip functionality, and successful delivery of complex semiconductor projects.
What are some common challenges Senior ASIC Design Engineers face when collaborating with cross-functional teams?
Senior ASIC Design Engineers often work closely with verification, software, and systems teams throughout the development cycle. One common challenge is ensuring clear communication of design specifications and changes, as misunderstandings can lead to integration issues or delays. Balancing multiple project timelines and adapting to evolving requirements from other departments can also be demanding. Building strong, collaborative relationships and using robust documentation and project management tools are key to overcoming these challenges.
What does a Senior ASIC Design Engineer do?
A Senior ASIC Design Engineer is responsible for designing and developing Application-Specific Integrated Circuits (ASICs) used in a wide range of electronic devices. They lead the architecture, implementation, and verification of complex digital or mixed-signal circuits, often collaborating with cross-functional teams. This senior role involves optimizing designs for performance, power, and area while ensuring that the final product meets stringent technical and quality requirements. Additionally, they may mentor junior engineers and contribute to design methodologies and best practices within the organization.
What is the difference between Senior Asic Design Engineer vs Digital IC Design Engineer?
| Aspect | Senior Asic Design Engineer | Digital IC Design Engineer |
|---|---|---|
| Required Credentials | Bachelor's/Master's in Electrical Engineering, VLSI, or related fields; experience in ASIC design | Bachelor's/Master's in Electrical Engineering, VLSI, or related fields; focus on digital circuit design |
| Work Environment | Design teams in semiconductor or tech companies, hardware development labs | Integrated circuit design teams, research labs, semiconductor companies |
| Employer & Industry Usage | Used in ASIC development, FPGA design, hardware acceleration | Used in digital chip design, FPGA development, digital system integration |
The main difference is that a Senior Asic Design Engineer specializes in designing application-specific integrated circuits, often leading complex projects, while a Digital IC Design Engineer focuses on digital circuit design within integrated circuits. Both roles require similar educational backgrounds and work environments but differ in project scope and specialization.
What are the most commonly searched types of Asic Design Engineer jobs in Arizona? The most popular types of Asic Design Engineer jobs in Arizona are:
What are popular job titles related to Senior Asic Design Engineer jobs in Arizona? For Senior Asic Design Engineer jobs in Arizona, the most frequently searched job titles are:
What job categories do people searching Senior Asic Design Engineer jobs in Arizona look for? The top searched job categories for Senior Asic Design Engineer jobs in Arizona are:
What cities in Arizona are hiring for Senior Asic Design Engineer jobs? Cities in Arizona with the most Senior Asic Design Engineer job openings:
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Full-time
Medical, Retirement, PTO
Posted 22 days ago
Intel rating
8.8
Based on 143 frontline employees who took The Breakroom Quiz
9th of 137 rated electronics manufacturers
Job description
Job Details:Job Description:
Intel Foundry is a systems foundry transforming the global semiconductor industry by delivering cutting-edge silicon process and packaging technology leadership for the AI era. Intel Foundry will be differentiated from other foundries by our world class industry-leading IP portfolio that customers can choose from including rich IP ecosystem including x86 cores, graphics, AI, and Arm/RISC-V IPs, world-class design services, and operationally resilient global manufacturing with committed capacity in the US and Europe.
Position Overview
We seek a Senior ASIC Design Engineer to provide technical support to Intel Foundry Services customers on PDKs through ASIC design implementation flows and to perform ASIC physical design execution with specialized focus on complex multi-voltage domain (UPF/CPF) designs and power-intent (VCLP and Conformal LP) verification signoff. This role drives quality improvements in design kits, supports customers through successful tape-outs, and performs ASIC design service on complex multi-voltage domain designs.
Key Responsibilities
Customer Technical Support and ASIC Design Execution
- Provide comprehensive technical support to Intel Foundry Services customers on PDKs, digital reference flows and digital design signoff methodologies in multi-voltage domain implementation and verification.
- Support and deliver ASIC/Digital tool/flow/methodology solutions, especially in multi-voltage domain design implementation and verification using Cadence and Synopsys tool suites. Have deep knowledge of UPF/CPF (level-shifter, isolation, power gating, retention, always-on) implementation and verification using (VCLP and Conformal LP). Have experience in writing and debugging UPF/CPF for multi-voltage domain designs.
- Drive customer success through expert guidance and have strong hand-on experience in ASIC design execution
Quality Assurance and Documentation
- Drive quality improvements in design kits and documentation through ASIC design reference flow validation and comprehensive documentation review
- Create application notes, technical design checklists, and deliver training presentations to customers and internal teams
- Establish and maintain high quality design through implementation and verification methodologies and checklists
Core Competencies
- Self-driven and results-oriented with ability to manage multiple tasks effectively
- Strong teamwork skills to drive solutions for implementation challenge
- Analytical problem-solving capabilities for complex design issues
- Excellent communication skills with experience in collaboration and customer feedback
The Minimum qualifications are required to be considered for this position. Minimum qualifications listed below would be obtained through a combination of industry relevant job experience, internship experience and / or schoolwork/classes/research. The preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
Minimum Qualifications
- US Citizenship required.
- Ability to obtain a US Government Security Clearance.
- Bachelor's degree in Electrical / Computer Engineering, Computer Science, or in a STEM related field of study.
- 4+ years of experience with advanced CMOS processes (16nm and below).
- 3+ years of experience in ASIC design implementing and verification in area of low power, multi-voltage domain
- 3+ years of experience in scripting languages like Python, Perl, Tcl, and/or shell scripting
Preferred Qualifications
- Active US Government Security Clearance with a minimum of Secret level
- Post Graduate degree in Electrical / Computer Engineering, Computer Science, or in a STEM related field of study
- Experience with state-of-the-art process technology (7nm and below)
- Hands-on experience in physical design Implementation and verification methodology for multi-voltage domain in SoC design
- Experience using EDA tools for multi-power domain design (UPF/CPF) implementation and power-intent verification (VCLP, Conformal LP) at block and at SOC level
- Experience in writing and debugging UPF/CPF for multi-voltage domain designs
- Customer-facing experience in technical support roles
# cj
Job Type:Experienced HireShift:Shift 1 (United States of America)Primary Location: US, Arizona, PhoenixAdditional Locations:US, California, Santa Clara, US, Oregon, HillsboroBusiness group:The Central Engineering Group (CEG) is Intel's data-driven organization that builds scalable engineering solutions across three pillars: Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom silicon), and Foundry Enablement (supporting top customers and validating technologies). The team focuses on customer-driven, end-to-end solutions with short development cycles to deliver measurable business impact across Intel's product and foundry businesses.Posting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of TrustN/ABenefitsWe offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.
Annual Salary Range for jobs which could be performed in the US: $122,440.00-232,190.00 USDThe range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.*
ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.
About Intel
Sourced by ZipRecruiter
Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore's Law to bring smart, connected devices to every person on Earth
Industry
Manufacturing
Company size
10,000+ Employees
Headquarters location
Santa Clara, CA, US
Year founded
1968