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Internship Asic Rtl Design Engineer Jobs in Arizona

RTL Design Engineer

Chandler, AZ · On-site

$127.10K - $203.40K/yr

Broadcom's Central Engineering Group is seeking a candidate to lead the digital design and ... Design convergence to timing closure utilizing RTL optimization strategies. * Conduct formal ...

RTL Design Engineer

Phoenix, AZ · On-site

$105.65K - $200.34K/yr

Develops the logic design, register transfer level (RTL) coding, and simulation for a CPU required ... Silicon and Platform Engineering Group (SPE): Deliver breakthrough silicon and platform solutions ...

RTL Design Engineer

Chandler, AZ · On-site

$127.10K - $203.40K/yr

Broadcom's Central Engineering Group is seeking a candidate to lead the digital design and ... Design convergence to timing closure utilizing RTL optimization strategies. * Conduct formal ...

The Role and Impact As a Senior RTL Design Engineer, you will play a pivotal role in developing Intel's next-generation microprocessors, contributing to groundbreaking technologies that drive ...

Digital Design Engineer

Chandler, AZ · On-site

$133.90K/yr

Develop RTL designs using Verilog and support integration into larger SoC environments. * Design ... Exposure to low-power and high-performance ASIC design techniques. * Experience with back-end flows ...

Senior Digital Design Engineer

Chandler, AZ · On-site

$133.90K/yr

Develop RTL designs using Verilog and support integration into larger SoC environments. * Design ... Exposure to low-power and high-performance ASIC design techniques. * Experience with back-end flows ...

Staff Digital Design Engineer

Chandler, AZ · On-site

$133.90K/yr

Develop RTL designs using Verilog and support integration into larger SoC environments. * Design ... Exposure to low-power and high-performance ASIC design techniques. * Experience with back-end flows ...

Develop the logic design and register transfer level (RTL) coding for CPU features. * Perform ... internship experiences Minimum Qualifications: * Bachelor's degree in Electrical Engineering ...

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Internship Asic Rtl Design Engineer information

What are the key skills and qualifications needed to thrive as an Internship ASIC RTL Design Engineer, and why are they important?

To thrive as an Internship ASIC RTL Design Engineer, you need a solid understanding of digital logic design, computer architecture, and proficiency in HDL languages like Verilog or VHDL, typically supported by coursework in electrical or computer engineering. Familiarity with industry-standard EDA tools such as Synopsys, Cadence, or Mentor Graphics, and simulation environments is highly valuable. Strong analytical thinking, attention to detail, and effective communication skills help interns collaborate with teams and learn quickly in a fast-paced environment. These skills and qualities are essential for contributing to complex chip design projects and ensuring accuracy and efficiency in RTL development.

What types of projects and responsibilities can an intern expect as an ASIC RTL Design Engineer?

As an ASIC RTL Design Engineering intern, you'll typically work on tasks such as writing and verifying RTL code using languages like Verilog or VHDL, assisting with simulation and debugging, and collaborating closely with senior engineers on real design blocks. Interns often participate in design reviews, update documentation, and may get hands-on experience with synthesis and timing analysis tools. This role is highly collaborative and provides exposure to the complete ASIC development cycle, making it an excellent opportunity to build foundational skills and gain insight into industry-standard methodologies.

What is an Internship ASIC RTL Design Engineer?

An Internship ASIC RTL (Register Transfer Level) Design Engineer is a student or recent graduate who assists in designing and developing digital integrated circuits (ICs) using hardware description languages like Verilog or VHDL. They work under the guidance of senior engineers to create, simulate, and verify RTL code for ASIC (Application Specific Integrated Circuit) projects. The role provides hands-on experience with the chip design process, including synthesis, timing analysis, and verification. Interns gain valuable exposure to industry-standard tools and methodologies, helping them prepare for a full-time engineering career.

What is the difference between Internship Asic Rtl Design Engineer vs Asic Verification Engineer?

AspectInternship Asic Rtl Design EngineerAsic Verification Engineer
CredentialsTypically pursuing or recently completed a degree in Electrical Engineering or Computer EngineeringSimilar educational background, often with additional coursework in verification methodologies
Work EnvironmentInternship setting, supervised, focused on learning and assisting in RTL design tasksFull-time role, focused on testing and verifying RTL designs
Industry UsageUsed in semiconductor and chip design companies during early career stagesCommon in companies developing complex integrated circuits and chips

The Internship Asic Rtl Design Engineer focuses on assisting in RTL design tasks during an internship, emphasizing learning and support. In contrast, the Asic Verification Engineer is responsible for verifying RTL designs to ensure functionality. Both roles require similar educational backgrounds but differ in responsibilities and work environment, with verification roles being more advanced and permanent.

What are the most commonly searched types of Asic Rtl Design Engineer jobs in Arizona? The most popular types of Asic Rtl Design Engineer jobs in Arizona are:
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RTL Design Engineer

RTL Design Engineer

Broadcom, Inc.

Chandler, AZ • On-site

$127.10K - $203.40K/yr

Full-time

Medical, Dental, Vision, Retirement, PTO

Posted 8 days ago


Broadcom rating

8.7

Company rating: 8.7 out of 10

Based on 23 frontline employees who took The Breakroom Quiz

12th of 137 rated electronics manufacturers


Job description

Please Note:
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Job Description:
Broadcom's Central Engineering Group is seeking a candidate to lead the digital design and verification of a broad range of analog mixed signal IP and IOs, including leading-edge AI programs on advanced nodes. Joining a world-class team of engineers with a highly collaborative culture, the role offers opportunities for growth and development.
  • Define the digital architecture and verification strategies for complex AMS and IO subsytems
  • Design, synthesis, and verification of Verilog/SystemVerilog RTL.
  • Analysis, debug, and resolution of Lint and CDC issues in the design.
  • Design convergence to timing closure utilizing RTL optimization strategies.
  • Conduct formal verification of design with Synopsys Formality / Cadence Conformal.
  • Generate timing constraints for Synthesis and STA at the block-level and SoC top-level.
  • Drive comprehensive test plans to ensure quality of design.
  • Collaborate with cross-functional teams, ranging from analog/mixed-signal circuit designers to SoC-level system integration.
  • Create and maintain detailed specification, design, and verification documentation.

Job Requirements
  • MS +10 years of relevant industry experience.
  • Experience with digital implementation flow from RTL synthesis to timing closure.
  • Deep understanding of timing analysis with Primetime flow and generation of Liberty models.
  • Experience with Tessent tool for DFT insertion and verification
  • Proficient with Perl, Python and Tcl scripting.
  • Strong problem solving skills with attention to detail.
  • Must be self-motivated and able to work effectively across internal and external engineering teams.

Highly Desired Qualifications
  • Solid understanding of transistor-level circuit behavior.
  • Familiar with Cadence Schematic/Layout, SPICE/Spectre circuit simulation.
  • Experience with advanced FinFET process nodes , including features, technology limitations and PPA tradeoffs.

Additional Job Description:
Compensation and Benefits
The annual base salary range for this position is $127,100 - $203,400.
This position is also eligible for a discretionary annual bonus in accordance with relevant plan documents, and equity in accordance with equity plan documents and equity award agreements.
Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.
Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.
If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.

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