CPU RTL Design Engineer
$141K - $269K/yr
Write RTL and optimize logic for power, performance, area, and timing goals. * Ensure design ... internship experiences. Minimum Qualifications: Bachelor's degree in electrical engineering ...
$141K - $269K/yr
Write RTL and optimize logic for power, performance, area, and timing goals. * Ensure design ... internship experiences. Minimum Qualifications: Bachelor's degree in electrical engineering ...
$141K - $269K/yr
Write RTL and optimize logic for power, performance, area, and timing goals. * Ensure design ... internship experiences. Minimum Qualifications: Bachelor's degree in electrical engineering ...
Chandler, AZ · On-site
$127K - $203K/yr
Broadcom's Central Engineering Group is seeking a candidate to lead the digital design and ... Design convergence to timing closure utilizing RTL optimization strategies. * Conduct formal ...
Chandler, AZ · On-site
$127K - $203K/yr
Broadcom's Central Engineering Group is seeking a candidate to lead the digital design and ... Design convergence to timing closure utilizing RTL optimization strategies. * Conduct formal ...
Chandler, AZ · On-site
$127K - $203K/yr
Broadcom's Central Engineering Group is seeking a candidate to lead the digital design and ... Design convergence to timing closure utilizing RTL optimization strategies. * Conduct formal ...
Chandler, AZ · On-site
$127K - $203K/yr
Broadcom's Central Engineering Group is seeking a candidate to lead the digital design and ... Design convergence to timing closure utilizing RTL optimization strategies. * Conduct formal ...
$164K - $269K/yr
As a Senior CPU RTL Design Engineer - Power Management , you will play a critical role in designing and delivering CPU microarchitectures with strong emphasis on power management and energy-efficient ...
$164K - $269K/yr
As a Senior CPU RTL Design Engineer - Power Management , you will play a critical role in designing and delivering CPU microarchitectures with strong emphasis on power management and energy-efficient ...
As a Principal Digital Design Engineer, the candidate shall be working with multi-sited global ... RTL design, design verification, synthesis, STA, and Test using an industry leading ASIC design ...
As a Principal Digital Design Engineer, the candidate shall be working with multi-sited global ... RTL design, design verification, synthesis, STA, and Test using an industry leading ASIC design ...
As a Principal Digital Design Engineer, the candidate shall be working with multi-sited global ... RTL design, design verification, synthesis, STA, and Test using an industry leading ASIC design ...
As a Principal Digital Design Engineer, the candidate shall be working with multi-sited global ... RTL design, design verification, synthesis, STA, and Test using an industry leading ASIC design ...
Chandler, AZ · On-site
$133K/yr
Develop RTL designs using Verilog and support integration into larger SoC environments. * Design ... Exposure to low-power and high-performance ASIC design techniques. * Experience with back-end flows ...
Chandler, AZ · On-site
$133K/yr
Develop RTL designs using Verilog and support integration into larger SoC environments. * Design ... Exposure to low-power and high-performance ASIC design techniques. * Experience with back-end flows ...
Tucson, AZ · On-site
$116K - $160K/yr
Develop RTL and support simulation, synthesis, place and route, timing closure, hardware ... Computer Engineering, or a related technical field. * 8+ years of professional FPGA design and ...
Tucson, AZ · On-site
$116K - $160K/yr
Develop RTL and support simulation, synthesis, place and route, timing closure, hardware ... Computer Engineering, or a related technical field. * 8+ years of professional FPGA design and ...
$116K - $160K/yr
Develop RTL and support simulation, synthesis, place and route, timing closure, hardware ... Computer Engineering, or a related technical field. * 8+ years of professional FPGA design and ...
$116K - $160K/yr
Develop RTL and support simulation, synthesis, place and route, timing closure, hardware ... Computer Engineering, or a related technical field. * 8+ years of professional FPGA design and ...
Chandler, AZ · On-site
$133K/yr
Develop RTL designs using Verilog and support integration into larger SoC environments. * Design ... Exposure to low-power and high-performance ASIC design techniques. * Experience with back-end flows ...
Chandler, AZ · On-site
$133K/yr
Develop RTL designs using Verilog and support integration into larger SoC environments. * Design ... Exposure to low-power and high-performance ASIC design techniques. * Experience with back-end flows ...
Tucson, AZ · On-site
$116K - $160K/yr
Develop RTL and support simulation, synthesis, place and route, timing closure, hardware ... Computer Engineering, or a related technical field. * 8+ years of professional FPGA design and ...
Quick apply
Tucson, AZ · On-site
$116K - $160K/yr
Develop RTL and support simulation, synthesis, place and route, timing closure, hardware ... Computer Engineering, or a related technical field. * 8+ years of professional FPGA design and ...
Chandler, AZ · On-site
$133K/yr
Develop RTL designs using Verilog and support integration into larger SoC environments. * Design ... Exposure to low-power and high-performance ASIC design techniques. * Experience with back-end flows ...
Chandler, AZ · On-site
$133K/yr
Develop RTL designs using Verilog and support integration into larger SoC environments. * Design ... Exposure to low-power and high-performance ASIC design techniques. * Experience with back-end flows ...
Chandler, AZ · On-site
$133K/yr
Develop RTL designs using Verilog and support integration into larger SoC environments. * Design ... Exposure to low-power and high-performance ASIC design techniques. * Experience with back-end flows ...
Chandler, AZ · On-site
$133K/yr
Develop RTL designs using Verilog and support integration into larger SoC environments. * Design ... Exposure to low-power and high-performance ASIC design techniques. * Experience with back-end flows ...
Chandler, AZ · On-site
This is a hands-on role spanning RTL design, integration, and signoff verification-with broad cross ... ASIC/SoC Digital Design and Verification * Strong foundations in digital logic / finite state ...
Chandler, AZ · On-site
This is a hands-on role spanning RTL design, integration, and signoff verification-with broad cross ... ASIC/SoC Digital Design and Verification * Strong foundations in digital logic / finite state ...
Chandler, AZ · On-site
This is a hands-on role spanning RTL design, integration, and signoff verification-with broad cross ... ASIC/SoC Digital Design and Verification * Strong foundations in digital logic / finite state ...
Chandler, AZ · On-site
This is a hands-on role spanning RTL design, integration, and signoff verification-with broad cross ... ASIC/SoC Digital Design and Verification * Strong foundations in digital logic / finite state ...
Chandler, AZ · On-site +1
$200K - $250K/yr
Head of Engineering About Us PowerLattice is a well-funded semiconductor start-up company backed by ... Actively contribute to RTL development for key components * Drive design tradeoffs across ...
Chandler, AZ · On-site +1
$200K - $250K/yr
Head of Engineering About Us PowerLattice is a well-funded semiconductor start-up company backed by ... Actively contribute to RTL development for key components * Drive design tradeoffs across ...
Scottsdale, AZ · On-site
$119K - $164K/yr
... ASIC (Application Specific Integrated Circuit) and/or FPGA (Field Programmable Gate Array ... RTL coding and be proficient in micro-architecture design. Successful candidates will have an ...
Scottsdale, AZ · On-site
$119K - $164K/yr
... ASIC (Application Specific Integrated Circuit) and/or FPGA (Field Programmable Gate Array ... RTL coding and be proficient in micro-architecture design. Successful candidates will have an ...
Scottsdale, AZ · On-site
$122K - $136K/yr
... ASIC (Application Specific Integrated Circuit) and/or FPGA (Field Programmable Gate Array ... RTL coding and be proficient in micro-architecture design. Successful candidates will have an ...
Scottsdale, AZ · On-site
$122K - $136K/yr
... ASIC (Application Specific Integrated Circuit) and/or FPGA (Field Programmable Gate Array ... RTL coding and be proficient in micro-architecture design. Successful candidates will have an ...
Proficient in RTL design (Verilog/System Verilog), Low-power design, synthesis, timing constraint ... Experience with ASIC design flow including LINT, Formal, CDC/RDC, power estimations, MBIST/DFT ...
Proficient in RTL design (Verilog/System Verilog), Low-power design, synthesis, timing constraint ... Experience with ASIC design flow including LINT, Formal, CDC/RDC, power estimations, MBIST/DFT ...
Implement specifications/designs in RTL and coordinate the work of other junior designers to ... Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom ...
Implement specifications/designs in RTL and coordinate the work of other junior designers to ... Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom ...
| Aspect | Internship Asic Rtl Design Engineer | Asic Verification Engineer |
|---|---|---|
| Credentials | Typically pursuing or recently completed a degree in Electrical Engineering or Computer Engineering | Similar educational background, often with additional coursework in verification methodologies |
| Work Environment | Internship setting, supervised, focused on learning and assisting in RTL design tasks | Full-time role, focused on testing and verifying RTL designs |
| Industry Usage | Used in semiconductor and chip design companies during early career stages | Common in companies developing complex integrated circuits and chips |
The Internship Asic Rtl Design Engineer focuses on assisting in RTL design tasks during an internship, emphasizing learning and support. In contrast, the Asic Verification Engineer is responsible for verifying RTL designs to ensure functionality. Both roles require similar educational backgrounds but differ in responsibilities and work environment, with verification roles being more advanced and permanent.
$141K - $269K/yr
Full-time
Medical, Retirement, PTO
Posted 20 days ago
8.7
Based on 145 frontline employees who took The Breakroom Quiz
10th of 141 rated electronics manufacturers
Intel put Silicon in Silicon Valley. No one else is obsessed with engineering and has a brighter future. Every day, we create world changing technology that enriches the lives of every person on earth. So, if you have a big idea, let's do something wonderful together. Join us, because at Intel, we are building a better tomorrow.
The Role and Impact:
As a CPU Logic Design Engineer, you will play a critical role in designing and optimizing the logic for Intel's cutting-edge processors. You will drive the development of register transfer level (RTL) code and simulation for the CPU, enabling creation of cell libraries, functional units, and CPU IP blocks for integration into full-chip designs. Your expertise will be pivotal in defining architecture and microarchitecture features, ensuring Intel continues to deliver innovative solutions that lead the industry in performance, energy efficiency, and design integrity. By contributing to the development and optimization of logic structures, you will help create technology that enriches the lives of every person on Earth, while enabling Intel to achieve its broader mission of engineering a brighter future.
Key Responsibilities:
You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Experience listed below would be obtained through a combination of your degree, research and or relevant previous job and or internship experiences.
Minimum Qualifications:
Bachelor's degree in electrical engineering, computer engineering, or computer science with 7+ years of relevant experience; OR Master's degree with 5+ years of experience; OR PhD with 2+ years of experience.
Preferred Qualifications:
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.
Annual Salary Range for jobs which could be performed in the US: $141,910.00-269,100.00 USDThe range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.*
ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.Sourced by ZipRecruiter
Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore's Law to bring smart, connected devices to every person on Earth
Manufacturing
10,000+ Employees
Santa Clara, CA, US
1968