Implement specifications/designs in RTL and coordinate the work of other junior designers to ... Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom ...
Implement specifications/designs in RTL and coordinate the work of other junior designers to ... Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom ...
Principal FPGA/ASIC Engineer - Level 3
Gilbert, AZ · On-site
$79K - $118K/yr
The Principal FPGA/ASIC Engineer will be responsible for research, requirements analysis and ... Proficiency in FPGA design flow including items such as RTL/gate level simulation, synthesis, place ...
Principal FPGA/ASIC Engineer - Level 3
Gilbert, AZ · On-site
$79K - $118K/yr
The Principal FPGA/ASIC Engineer will be responsible for research, requirements analysis and ... Proficiency in FPGA design flow including items such as RTL/gate level simulation, synthesis, place ...
Senior FPGA Design Engineer
Chandler, AZ · On-site
$101K - $136K/yr
Strong digital design engineer with FPGA/ASIC SoC design experience * Strong FPGA Implementation ... Capable of creating RTL simulations to identify and resolve most issues before hardware tests
Quick apply
Senior FPGA Design Engineer
Chandler, AZ · On-site
$101K - $136K/yr
Strong digital design engineer with FPGA/ASIC SoC design experience * Strong FPGA Implementation ... Capable of creating RTL simulations to identify and resolve most issues before hardware tests
Proficient in RTL design (Verilog/System Verilog), Low-power design, synthesis, timing constraint ... Experience with ASIC design flow including LINT, Formal, CDC/RDC, power estimations, MBIST/DFT ...
Proficient in RTL design (Verilog/System Verilog), Low-power design, synthesis, timing constraint ... Experience with ASIC design flow including LINT, Formal, CDC/RDC, power estimations, MBIST/DFT ...
Position Overview We seek a Senior ASIC Design Engineer to provide technical support to Intel ... experience, internship experience and / or schoolwork/classes/research. The preferred ...
Position Overview We seek a Senior ASIC Design Engineer to provide technical support to Intel ... experience, internship experience and / or schoolwork/classes/research. The preferred ...
Principal Engineer Electrical
Gilbert, AZ · On-site
$98K - $147K/yr
HDL design for FPGA and/or ASIC applications * FPGA/ASIC verification via simulation and emulation ... Experience in RTL design for an aerospace environment or space application * Proficient in FPGA ...
Principal Engineer Electrical
Gilbert, AZ · On-site
$98K - $147K/yr
HDL design for FPGA and/or ASIC applications * FPGA/ASIC verification via simulation and emulation ... Experience in RTL design for an aerospace environment or space application * Proficient in FPGA ...
Position Overview We seek a Senior ASIC Design Engineer to provide technical support to Intel ... experience, internship experience and / or schoolwork/classes/research. The preferred ...
Position Overview We seek a Senior ASIC Design Engineer to provide technical support to Intel ... experience, internship experience and / or schoolwork/classes/research. The preferred ...
Principal Engineer Electrical
Gilbert, AZ · On-site
$98K - $147K/yr
HDL design for FPGA and/or ASIC applications * FPGA/ASIC verification via simulation and emulation ... Experience in RTL design for an aerospace environment or space application * Proficient in FPGA ...
Principal Engineer Electrical
Gilbert, AZ · On-site
$98K - $147K/yr
HDL design for FPGA and/or ASIC applications * FPGA/ASIC verification via simulation and emulation ... Experience in RTL design for an aerospace environment or space application * Proficient in FPGA ...
Principal Engineer, Digital Design Engineer (AI/ML)
Chandler, AZ · On-site
$198K/yr
As a Principal Digital Design Engineer, you will lead the architecture and implementation of ... Lead RTL design, coding, and optimization in Verilog/SystemVerilog for performance, area, and power ...
Principal Engineer, Digital Design Engineer (AI/ML)
Chandler, AZ · On-site
$198K/yr
As a Principal Digital Design Engineer, you will lead the architecture and implementation of ... Lead RTL design, coding, and optimization in Verilog/SystemVerilog for performance, area, and power ...
As a Staff Digital Design Engineer, you will develop complex digital subsystems within ADI's mixed ... Execute RTL design, coding, and optimization in Verilog/SystemVerilog for performance, area, and ...
As a Staff Digital Design Engineer, you will develop complex digital subsystems within ADI's mixed ... Execute RTL design, coding, and optimization in Verilog/SystemVerilog for performance, area, and ...
As a Staff Digital Design Engineer, you will develop complex digital subsystems within ADI's mixed ... Execute RTL design, coding, and optimization in Verilog/SystemVerilog for performance, area, and ...
As a Staff Digital Design Engineer, you will develop complex digital subsystems within ADI's mixed ... Execute RTL design, coding, and optimization in Verilog/SystemVerilog for performance, area, and ...
As a Principal Digital Design Engineer, you will lead the architecture and implementation of ... Lead RTL design, coding, and optimization in Verilog/SystemVerilog for performance, area, and power ...
As a Principal Digital Design Engineer, you will lead the architecture and implementation of ... Lead RTL design, coding, and optimization in Verilog/SystemVerilog for performance, area, and power ...
Complete high-quality, area-optimal, low-power RTL design using industry-standard hardware ... Collaborate with architects, analog designers, test/product/quality/bench engineers and software ...
Complete high-quality, area-optimal, low-power RTL design using industry-standard hardware ... Collaborate with architects, analog designers, test/product/quality/bench engineers and software ...
Physical Design Engineer
Phoenix, AZ · On-site
$135K - $139K/yr
... ASIC/SoC design Min. * Qualifications: 0-1 yrs of exp. Enginner - CL11 & CL10 Master's degree in Electrical Eng. or Comp. Science RTL2GDSII exp. on advanced tech. nodes (7nm and below) Exp. w/low ...
Physical Design Engineer
Phoenix, AZ · On-site
$135K - $139K/yr
... ASIC/SoC design Min. * Qualifications: 0-1 yrs of exp. Enginner - CL11 & CL10 Master's degree in Electrical Eng. or Comp. Science RTL2GDSII exp. on advanced tech. nodes (7nm and below) Exp. w/low ...
Digital Design Engineer 4
Tucson, AZ · On-site
$175K/yr
Join Legion Technical Solutions LLC as a Digital Design Engineer 4 in Tucson, AZ, where innovation ... Proficiency in FPGA and ASIC design tools. * Strong understanding of digital signal processing ...
Quick apply
Digital Design Engineer 4
Tucson, AZ · On-site
$175K/yr
Join Legion Technical Solutions LLC as a Digital Design Engineer 4 in Tucson, AZ, where innovation ... Proficiency in FPGA and ASIC design tools. * Strong understanding of digital signal processing ...
Digital Design Engineer
Tucson, AZ · On-site
$165K/yr
Join Legion Technical Solutions LLC as a Digital Design Engineer in Tucson, AZ, where innovation ... Strong knowledge of FPGA and ASIC design methodologies. * Proficiency in design software such as ...
Quick apply
Digital Design Engineer
Tucson, AZ · On-site
$165K/yr
Join Legion Technical Solutions LLC as a Digital Design Engineer in Tucson, AZ, where innovation ... Strong knowledge of FPGA and ASIC design methodologies. * Proficiency in design software such as ...
Senior FPGA Design Engineer
$122K - $168K/yr
As a Senior FPGA Design Engineer you will develop FPGA designs for all major vendors and device ... FPGA/ASIC design, including VHDL and/or Verilog coding or FPGA/ASIC verification using ...
Senior FPGA Design Engineer
$122K - $168K/yr
As a Senior FPGA Design Engineer you will develop FPGA designs for all major vendors and device ... FPGA/ASIC design, including VHDL and/or Verilog coding or FPGA/ASIC verification using ...
Senior Design Verification Engineer
Tempe, AZ · On-site
$176K - $264K/yr
As a Design Verification Engineer, you will be part of a verification team responsible for the full cycle of RTL verification for FPGA and ASIC designs. You will be responsible for: * Design ...
Senior Design Verification Engineer
Tempe, AZ · On-site
$176K - $264K/yr
As a Design Verification Engineer, you will be part of a verification team responsible for the full cycle of RTL verification for FPGA and ASIC designs. You will be responsible for: * Design ...
Senior FPGA Design Engineer
$116K - $160K/yr
As a Senior FPGA Design Engineer you will develop FPGA designs for all major vendors and device ... FPGA/ASIC design, including VHDL and/or Verilog coding or FPGA/ASIC verification using ...
Senior FPGA Design Engineer
$116K - $160K/yr
As a Senior FPGA Design Engineer you will develop FPGA designs for all major vendors and device ... FPGA/ASIC design, including VHDL and/or Verilog coding or FPGA/ASIC verification using ...
Senior FPGA Design Engineer
$116K - $160K/yr
As a Senior FPGA Design Engineer you will develop FPGA designs for all major vendors and device ... FPGA/ASIC design, including VHDL and/or Verilog coding or FPGA/ASIC verification using ...
Senior FPGA Design Engineer
$116K - $160K/yr
As a Senior FPGA Design Engineer you will develop FPGA designs for all major vendors and device ... FPGA/ASIC design, including VHDL and/or Verilog coding or FPGA/ASIC verification using ...
Internship Asic Rtl Design Engineer information
What types of projects and responsibilities can an intern expect as an ASIC RTL Design Engineer?
As an ASIC RTL Design Engineering intern, you'll typically work on tasks such as writing and verifying RTL code using languages like Verilog or VHDL, assisting with simulation and debugging, and collaborating closely with senior engineers on real design blocks. Interns often participate in design reviews, update documentation, and may get hands-on experience with synthesis and timing analysis tools. This role is highly collaborative and provides exposure to the complete ASIC development cycle, making it an excellent opportunity to build foundational skills and gain insight into industry-standard methodologies.
What are the key skills and qualifications needed to thrive as an Internship ASIC RTL Design Engineer, and why are they important?
To thrive as an Internship ASIC RTL Design Engineer, you need a solid understanding of digital logic design, computer architecture, and proficiency in HDL languages like Verilog or VHDL, typically supported by coursework in electrical or computer engineering. Familiarity with industry-standard EDA tools such as Synopsys, Cadence, or Mentor Graphics, and simulation environments is highly valuable. Strong analytical thinking, attention to detail, and effective communication skills help interns collaborate with teams and learn quickly in a fast-paced environment. These skills and qualities are essential for contributing to complex chip design projects and ensuring accuracy and efficiency in RTL development.
What is an Internship ASIC RTL Design Engineer?
An Internship ASIC RTL (Register Transfer Level) Design Engineer is a student or recent graduate who assists in designing and developing digital integrated circuits (ICs) using hardware description languages like Verilog or VHDL. They work under the guidance of senior engineers to create, simulate, and verify RTL code for ASIC (Application Specific Integrated Circuit) projects. The role provides hands-on experience with the chip design process, including synthesis, timing analysis, and verification. Interns gain valuable exposure to industry-standard tools and methodologies, helping them prepare for a full-time engineering career.
What is the difference between Internship Asic Rtl Design Engineer vs Asic Verification Engineer?
| Aspect | Internship Asic Rtl Design Engineer | Asic Verification Engineer |
|---|---|---|
| Credentials | Typically pursuing or recently completed a degree in Electrical Engineering or Computer Engineering | Similar educational background, often with additional coursework in verification methodologies |
| Work Environment | Internship setting, supervised, focused on learning and assisting in RTL design tasks | Full-time role, focused on testing and verifying RTL designs |
| Industry Usage | Used in semiconductor and chip design companies during early career stages | Common in companies developing complex integrated circuits and chips |
The Internship Asic Rtl Design Engineer focuses on assisting in RTL design tasks during an internship, emphasizing learning and support. In contrast, the Asic Verification Engineer is responsible for verifying RTL designs to ensure functionality. Both roles require similar educational backgrounds but differ in responsibilities and work environment, with verification roles being more advanced and permanent.
What are the most commonly searched types of Asic Rtl Design Engineer jobs in Arizona? The most popular types of Asic Rtl Design Engineer jobs in Arizona are:
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Full-time
Medical, Retirement, PTO
Posted 7 days ago
Intel rating
8.7
Based on 145 frontline employees who took The Breakroom Quiz
10th of 141 rated electronics manufacturers
Job description
Job Details:Job Description:
As a Mixed Signal Logic Design Engineer, you will play a pivotal role in shaping the future of high-speed and mixed signal IP designs at Intel. Your contributions will directly impact the development of cutting-edge technologies that enable the integration of functional units, IP blocks, and subsystems into full chip designs. This position is at the forefront of innovation, requiring collaboration with cross-functional teams to define architecture and microarchitecture features, optimize performance, and ensure design integrity. Your work will drive Intel's success in achieving power, performance, and area goals, empowering our customers with industry-leading solutions.
Key Responsibilities:
Develop architecture and microarchitecture specifications for the logic components and contribute to the overall system architecture decisions
Implement specifications/designs in RTL and coordinate the work of other junior designers to deliver high-quality, complex logic blocks
Develop behavioral models that represent analog and mixed-signal circuit blocks using SystemVerilog
Run simulations and debug using logic, mixed-signal validation and AMS simulation tools
Ensure high-quality designs by using industry standard tools such as linting and CDC analysis
Support the physical design team in implementing your designs, including synthesis and timing closure
Work with the pre-silicon validation/verification team to develop test plans and verification collateral
Work with post-silicon validation teams to resolve post-silicon issues
You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Knowledge and/or experience listed below would be obtained through a combination of your school, work and/or classes and/or research and/or relevant previous job and/or internship experiences.
Minimum Qualifications:
- BS degree in Electrical Engineering or Computer Engineering or similar field of study with 4+ years relevant experience
- -OR- MS degree in Electrical Engineering or Computer Engineering or similar field of study with 3+ years relevant experience.
- Experience with standard digital design concepts such as FSM design techniques
- Experience with SystemVerilog
- Experience with computer architecture, analog design, ADC/DAC designs, communications theory, and/or microarchitecture design concepts
- Experience producing high-level architecture that meets internal and industry-standard specifications.
- Comfortable working with a high level of independence.
- Experience with multiple clock-domain design
Preferred Qualifications:
- BS degree in Electrical Engineering or Computer Engineering or similar field of study with 10+ years relevant experience
- -OR- MS degree in Electrical Engineering or Computer Engineering or similar field of study with 8+ years relevant experience.
- Able to work highly independently, guide other junior team members and make contributions that increase the productivity of the entire design team
- Excellent communication and interpersonal skills
- Experience with both logic and analog circuits as well as with analog behavioral modeling
- Knowledge of mixed-signal validation, signal and systems analysis
- Knowledge of High-Speed I/O protocol stacks (UCIe, PCIe, USB, etc.)
- Experience with scripting languages e.g. Perl, bash/csh and Python is highly desirable
- Proven record of coordinating/guiding other designers to deliver large complex logic blocks
- Experience using RTL quality tools such as linting and CDC analysis and supporting team adoption and usage
- Experience with low-power design, power gating and multiple power-domain design
- Experience with writing, testing, packaging and releasing firmware
- Experience writing, testing and supporting front-end automation and packaging flows
- Experience using AI tools as a productivity booster in all aspects of the IP design process
- Strong analytical debugging skills, with a creative approach to problem-solving
Join us in redefining technology and engineering challenges. Apply today and become part of a team where your expertise drives meaningful change and innovation.
Job Type:College GradShift:Shift 1 (United States of America)Primary Location: US, Oregon, HillsboroAdditional Locations:US, Arizona, Phoenix, US, California, Santa ClaraBusiness group:The Central Engineering Group (CEG) is Intel's data-driven organization that builds scalable engineering solutions across three pillars: Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom silicon), and Foundry Enablement (supporting top customers and validating technologies). The team focuses on customer-driven, end-to-end solutions with short development cycles to deliver measurable business impact across Intel's product and foundry businesses.Posting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of TrustN/ABenefitsWe offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.
Annual Salary Range for jobs which could be performed in the US: $141,910.00-269,100.00 USDThe range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.Work Model for this Role
This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.*
ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.
About Intel
Sourced by ZipRecruiter
Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore's Law to bring smart, connected devices to every person on Earth
Industry
Manufacturing
Company size
10,000+ Employees
Headquarters location
Santa Clara, CA, US
Year founded
1968