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Internship Asic Rtl Design Engineer Jobs in Arizona

Collaborate with RTL and Hard IP designers on DFT/DFM implementation methodology and work with ... Hands-on experience in Design Implementation and methodology (ASIC design, Fullchip Integration ...

Collaborate with RTL and Hard IP designers on DFT/DFM implementation methodology and work with ... Hands-on experience in Design Implementation and methodology (ASIC design, Fullchip Integration ...

Lead FPGA Design Engineer

Phoenix, AZ · Hybrid

$122.10K - $168.30K/yr

... software engineers during planning, requirements and architecture, design, test and integration ... of ASIC /FPGA Radiation Hardening techniques - Strong technical and project and problem-solving ...

Package Design Engineer

Chandler, AZ · On-site

$133.90K/yr

... ASIC designers to develop a portfolio of packages that meets a huge range of performance design ... every stage - from internship to retirement and through life's most important moments. Our ...

Digital IC Design Engineer

Tucson, AZ · On-site

$116.90K/yr

Your responsibilities will include RTL coding, simulation, synthesis, timing closure, verification ... As a design engineer, you will prepare test methods and specifications, assist in preparation of ...

Debug and rootcause complex RTL, microarchitecture, and integration issues; drive issues to ... physical design engineers to improve design quality and verification effectiveness. * Influence ...

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Internship Asic Rtl Design Engineer information

What are the key skills and qualifications needed to thrive as an Internship ASIC RTL Design Engineer, and why are they important?

To thrive as an Internship ASIC RTL Design Engineer, you need a solid understanding of digital logic design, computer architecture, and proficiency in HDL languages like Verilog or VHDL, typically supported by coursework in electrical or computer engineering. Familiarity with industry-standard EDA tools such as Synopsys, Cadence, or Mentor Graphics, and simulation environments is highly valuable. Strong analytical thinking, attention to detail, and effective communication skills help interns collaborate with teams and learn quickly in a fast-paced environment. These skills and qualities are essential for contributing to complex chip design projects and ensuring accuracy and efficiency in RTL development.

What types of projects and responsibilities can an intern expect as an ASIC RTL Design Engineer?

As an ASIC RTL Design Engineering intern, you'll typically work on tasks such as writing and verifying RTL code using languages like Verilog or VHDL, assisting with simulation and debugging, and collaborating closely with senior engineers on real design blocks. Interns often participate in design reviews, update documentation, and may get hands-on experience with synthesis and timing analysis tools. This role is highly collaborative and provides exposure to the complete ASIC development cycle, making it an excellent opportunity to build foundational skills and gain insight into industry-standard methodologies.

What is an Internship ASIC RTL Design Engineer?

An Internship ASIC RTL (Register Transfer Level) Design Engineer is a student or recent graduate who assists in designing and developing digital integrated circuits (ICs) using hardware description languages like Verilog or VHDL. They work under the guidance of senior engineers to create, simulate, and verify RTL code for ASIC (Application Specific Integrated Circuit) projects. The role provides hands-on experience with the chip design process, including synthesis, timing analysis, and verification. Interns gain valuable exposure to industry-standard tools and methodologies, helping them prepare for a full-time engineering career.

What is the difference between Internship Asic Rtl Design Engineer vs Asic Verification Engineer?

AspectInternship Asic Rtl Design EngineerAsic Verification Engineer
CredentialsTypically pursuing or recently completed a degree in Electrical Engineering or Computer EngineeringSimilar educational background, often with additional coursework in verification methodologies
Work EnvironmentInternship setting, supervised, focused on learning and assisting in RTL design tasksFull-time role, focused on testing and verifying RTL designs
Industry UsageUsed in semiconductor and chip design companies during early career stagesCommon in companies developing complex integrated circuits and chips

The Internship Asic Rtl Design Engineer focuses on assisting in RTL design tasks during an internship, emphasizing learning and support. In contrast, the Asic Verification Engineer is responsible for verifying RTL designs to ensure functionality. Both roles require similar educational backgrounds but differ in responsibilities and work environment, with verification roles being more advanced and permanent.

What are the most commonly searched types of Asic Rtl Design Engineer jobs in Arizona? The most popular types of Asic Rtl Design Engineer jobs in Arizona are:
What job categories do people searching Internship Asic Rtl Design Engineer jobs in Arizona look for? The top searched job categories for Internship Asic Rtl Design Engineer jobs in Arizona are:
What cities in Arizona are hiring for Internship Asic Rtl Design Engineer jobs? Cities in Arizona with the most Internship Asic Rtl Design Engineer job openings:
IP Enablement Application Engineer

IP Enablement Application Engineer

Intel Corporation

Phoenix, AZ • On-site

Full-time

Medical, Retirement, PTO

Posted 18 days ago


Intel rating

8.8

Company rating: 8.8 out of 10

Based on 143 frontline employees who took The Breakroom Quiz

9th of 137 rated electronics manufacturers


Job description

Job Details:
Job Description:
About Intel Foundry Services
Intel Foundry is a systems foundry dedicated to transforming the global semiconductor industry by delivering cutting-edge silicon process and packaging technology leadership for the AI era. With a focus on scalability, AI advancement, and shaping the future, we provide an unparalleled blend of an industry-leading technology, a rich IP portfolio, a world-class design ecosystem, and an operationally resilient global manufacturing supply chain.
Position Overview
The Aerospace, Defense & Government (ADG) IP Enablement Application Engineer provides comprehensive technical support to Intel Foundry Services customers on IP integration challenges. This dynamic role requires a versatile engineer who engages with IP design teams and internal/external customers across all phases of IP development - from architecture through post-silicon validation and debug. The position embodies customer obsession by quickly resolving issues and providing hands-on debug across all design domains.
Key Responsibilities
IP Integration & Customer Support
  • Provide comprehensive technical support to Intel Foundry Services customers on IP integration issues, working independently with design teams and customers to solve complex challenges remotely or onsite
  • Fully own assigned IPs and work with internal and external customers to help them integrate Intel IPs into SoCs, providing expert technical support throughout the integration process
  • Drive resolution of customer issues related to IP collaterals generation, logic design verification, IP release, and integration in SoC environments

Cross-Functional Collaboration & IP Development
  • Work with cross-functional teams to develop SoC and IP integration methodologies and best practices
  • Engage with IP development teams to ensure all IP collaterals are generated and provided according to customer requirements and industry standards
  • Collaborate with internal teams across Intel and external stakeholders including foundry customers' design teams, IP providers, and EDA vendors on foundational IP integration issue resolution

Customer Requirements & Training
  • Engage in upfront identification and documentation of customer requirements, working with IP design teams to disposition and address requests
  • Prepare comprehensive customer training materials and provide training on IP architecture, specifications, and fuse/register settings to enable effective debug
  • Create application notes, documentation, and deliver technical training presentations to customers and internal teams

Quality & Process Improvement
  • Drive quality improvements in design kits and documentation, assisting in removing barriers to successful customer design tape-outs
  • Support debugging and problem-solving activities in collaborative team environments
  • Contribute to methodology improvements that enhance IP integration productivity and customer satisfaction

Core Competencies
  • Strong technical problem-solving and debugging capabilities
  • Ability to work independently and manage customer relationships effectively
  • Excellent communication skills for technical training and customer support
  • Willingness to travel to customer sites as required

Qualifications:
The Minimum qualifications are required to be considered for this position. Minimum qualifications listed below would be obtained through a combination of industry relevant job experience, internship experience and / or schoolwork/classes/research. The preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates
Minimum Qualifications
  • US Citizenship required
  • Ability to obtain a US Government Security Clearance
  • Bachelor's degree in Electrical Engineering, Computer Science, or in a STEM related field of study
  • 2+ years of experience in SOC IP Integration
  • 3+ years of combined experience in RTL design and DFT using Verilog/System Verilog
  • Experience in ASIC or SoC development

Preferred Qualifications:
  • Active US Government Security Clearance with a minimum of Secret level
  • Post Graduate degree in Electrical Engineering, Computer Science, or in a STEM related field of study
  • Experience with one or more industry standard IO interfaces including (ADPLL, GPIO, Digital Thermal Sensors, DDR, LPDDR, PCIE, USB, USB TypeC, Ethernet, etc.)
  • Experience with VCS, Verdi, Spyglass or equivalent tools
  • Experience with IP integration and design flow challenges within the context of subsystems and SOCs
  • Experience with IP development
  • Experience in scripting languages like such as Perl/Tcl/ and Python

What We Offer
  • Opportunity to work with cutting-edge memory technologies for aerospace, defense, and government applications
  • Direct customer engagement and technical leadership in advanced memory design
  • Access to Intel's most advanced foundry technologies and comprehensive memory IP portfolio
  • Competitive compensation
  • Professional development in memory design methodologies and foundry services
  • Direct impact on national security through advanced memory semiconductor solutions

Job Type:
Experienced Hire
Shift:
Shift 1 (United States of America)
Primary Location:
US, Arizona, Phoenix
Additional Locations:
US, California, Santa Clara, US, Oregon, Hillsboro
Business group:
The Central Engineering Group (CEG) is Intel's data-driven organization that builds scalable engineering solutions across three pillars: Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom silicon), and Foundry Enablement (supporting top customers and validating technologies). The team focuses on customer-driven, end-to-end solutions with short development cycles to deliver measurable business impact across Intel's product and foundry businesses.
Posting Statement:
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Position of Trust
N/A
Benefits
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.
Annual Salary Range for jobs which could be performed in the US: $122,440.00-232,190.00 USD
The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.
Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.
ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.

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About Intel

Sourced by ZipRecruiter

Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore's Law to bring smart, connected devices to every person on Earth

Industry

Manufacturing

Company size

10,000+ Employees

Headquarters location

Santa Clara, CA, US

Year founded

1968