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Remote Asic Rtl Design Engineer Jobs in Arizona (NOW HIRING)

Renesas Electronics

Senior Digital Engineer

Chandler, AZ · On-site +1

$133K/yr

... SystemVerilog RTL for digital CMOS circuit design. * Strong understanding of ASIC design ... Our people-first culture and global support system, including the remote work option and Employee ...

Renesas Electronics

Senior Digital Engineer

Chandler, AZ · On-site +1

$133K/yr

... SystemVerilog RTL for digital CMOS circuit design. * Strong understanding of ASIC design ... Our people-first culture and global support system, including the remote work option and Employee ...

YO AI Labs

Hardware Expert - Remote

Phoenix, AZ · Remote

$50 - $100/hr

Interpret engineering drawings and create accurate 3D CAD models. * Develop complex mechanical ... RTL * 3D Mechanical Modeling * Computational Geometry Qualifications * Strong experience with CAD ...

Renesas Electronics

Staff Analog Design Engineer

Chandler, AZ · On-site +1

$198K/yr

We are seeking a Staff Analog Design Engineer to drive the design of complex Power Management ICs ... Our people-first culture and global support system, including the remote work option and Employee ...

Renesas Electronics

Staff Analog Design Engineer

Chandler, AZ · On-site +1

$198K/yr

We are seeking a Staff Analog Design Engineer to drive the design of complex Power Management ICs ... Our people-first culture and global support system, including the remote work option and Employee ...

Lochner

Airport Design Engineer

Mesa, AZ · On-site +1

Design of airport engineering projects including runways, taxiways, aprons, airfield lighting ... Flexible work arrangements, including hybrid and remote opportunities where business needs allow

Qorvo, Inc.

Staff RFIC Design Engineer

Chandler, AZ · On-site +1

$144K - $187K/yr

Switch/LNA/RF IC Design Engineer, the design of GaAs/SOI/SiGe/CMOS based switch and LNA or RFIC ... Experience supporting remote engineering teams. * Be able to work independently, communicate well ...

Lochner

Senior Airport Design Engineer

Mesa, AZ · On-site +1

$89K - $123K/yr

As a Design Engineer, you can experience the following: * National and International Aviation ... remote opportunities where business needs allow • Life insurance and disability coverage ...

YO AI Labs

Autodesk Fusion 360 Expert - Remote

Phoenix, AZ · On-site +1

$40 - $120/hr

Remote Job Overview We are seeking experienced Autodesk Fusion 360 Specialists to contribute their ... No prior AI experience is required--your engineering and CAD expertise are what matter most. Key ...

YO AI Labs

Autodesk Inventor Expert - Remote

Phoenix, AZ · On-site +1

$30 - $120/hr

Remote Job Overview We are seeking experienced Autodesk Inventor Specialists to contribute their ... No prior AI experience is required--your engineering and CAD expertise are what matter most. Key ...

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Remote Asic Rtl Design Engineer information

What is a remote ASIC RTL design engineer?

A Remote ASIC RTL Design Engineer is a professional who specializes in designing the Register Transfer Level (RTL) code for Application-Specific Integrated Circuits (ASICs) while working remotely. Their main responsibilities include creating and verifying digital circuit designs using hardware description languages such as Verilog or VHDL. These engineers collaborate with hardware teams to ensure functionality, performance, and power requirements are met, all while operating from a location outside of a traditional office setting. They often use remote collaboration tools and simulation software to review and validate designs before fabrication.

What are the key skills and qualifications needed to thrive as a remote ASIC RTL design engineer?

To thrive as a Remote ASIC RTL Design Engineer, you need a solid background in digital design, computer engineering, and hardware description languages like Verilog or VHDL, often supported by a relevant degree. Proficiency with industry-standard EDA tools such as Synopsys, Cadence, or Mentor Graphics, as well as experience with simulation, synthesis, and version control systems, is crucial. Strong problem-solving, self-motivation, and effective remote communication skills distinguish top performers in this role. These skills ensure accurate, efficient design cycles and effective collaboration across distributed teams, leading to successful chip delivery.

What are some common challenges faced by remote ASIC RTL design engineers, and how can they be addressed?

Remote ASIC RTL Design Engineers often face challenges such as coordinating with distributed teams across different time zones and ensuring effective communication during complex design phases. To address these issues, it’s important to establish clear documentation practices, utilize collaboration tools like version control and video conferencing, and schedule regular check-ins with team members. Additionally, staying proactive in seeking feedback and clarifying design specifications helps ensure alignment and reduces misunderstandings. Building strong virtual relationships with verification and backend teams can also streamline the handoff process and overall project flow.

What is the difference between Remote Asic Rtl Design Engineer vs Remote Digital IC Design Engineer?

AspectRemote Asic Rtl Design EngineerRemote Digital IC Design Engineer
Primary FocusRegister Transfer Level (RTL) design for ASICsDigital integrated circuit design at the IC level
Skills & CertificationsHDL (Verilog/VHDL), EDA tools, verificationHDL, circuit simulation, verification, FPGA experience
Work EnvironmentASIC design teams, hardware developmentIC design teams, semiconductor industry
Industry UsageUsed in ASIC development for various applicationsUsed in digital IC manufacturing and prototyping

Both roles involve digital design and HDL skills, but the Remote Asic Rtl Design Engineer focuses on RTL coding for ASICs, while the Remote Digital IC Design Engineer covers broader digital IC design, including FPGA and chip-level work. They share similar credentials and work environments, often overlapping in semiconductor companies.

What are the most commonly searched types of Asic Rtl Design Engineer jobs in Arizona?

The most popular types of Asic Rtl Design Engineer jobs in Arizona are:

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For Remote Asic Rtl Design Engineer jobs in Arizona, the most frequently searched job titles are:

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The top searched job categories for Remote Asic Rtl Design Engineer jobs in Arizona are:

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Cities in Arizona with the most Remote Asic Rtl Design Engineer job openings:

Remote Asic Rtl Design Engineer jobs near you

Sr Physical Design Engineer (Synopsys Fusion / GF 12LP) - Remote - Full Time / Contract

Chandler, AZ • On-site, Remote

Encore Semi, Inc.
Semiconductor and Electronic Component Manufacturing • 51 - 200 employees
Learn more about Encore Semi, Inc.external

$150K - $165K/yr

Full-time

Medical, Dental, Vision, Life, Retirement, PTO

Posted 2 days ago

New

Job description

Sr Physical Design Engineer (Synopsys Fusion / GF 12LP) - Remote - Full Time / Contract
Full-time: Salary + Benefits + Bonuses / Contractor
Work Status: US Citizen or Lawful Permanent Resident.
We have an immediate need for an expert Physical Design Engineer to drive a high-speed design across the finish line. You will be working on a 1GHz AES hard macro targeted for the GlobalFoundries 12LP (12nm FinFET) process node. The design is nearly complete; your primary objective upon joining will be the final cleanup of 7 remaining DRC/ERC errors, completing fill insertion, and executing the final Calibre signoff checks for tape-out.
Core Technical Environment & Ongoing Responsibilities: Beyond this immediate milestone, you will take ownership of the RTL-to-GDSII flow for our next-generation SoCs, pushing the limits of Power, Performance, and Area (PPA).
  • Implementation: Execute block-level and top-level physical design (floorplanning, CTS, routing) using the Synopsys Fusion Design Platform (Fusion Compiler).
  • Timing & Signoff: Drive STA, parasitic extraction, and timing closure across multiple corners using PrimeTime and StarRC.
  • FinFET Optimization: Address 12nm FinFET challenges including advanced routing rules, EM/IR-drop analysis (Ansys RedHawk), and complex SDC constraint management.
  • Verification: Perform DRC, LVS, and antenna checks using Calibre and Synopsys IC Validator (ICV).
  • Automation: Maintain robust Tcl, Python, or Perl scripts to automate workflows.
Qualifications:
  • 10+ years of industry experience in ASIC physical design with successful tape-outs on advanced FinFET nodes (14nm/12nm/7nm).
  • Deep expertise in rapid DRC/LVS/ERC closure and final tape-out procedures.
  • Hands-on mastery of Synopsys Fusion Compiler (or ICC2) and PrimeTime.
  • Strong scripting skills (Tcl, Python, Bash).
  • Preferred: Direct experience with the GlobalFoundries 12LP/12LP+ node and Mentor Calibre.

The anticipated annual base salary for this position is between $150,000 to $165,000, which also includes a comprehensive benefits package.
Full-Time Benefits:
•15 days of PTO per calendar year
•10 paid Holidays per calendar year
•Comprehensive Medical Benefits: Company covers 80% of premiums for Employee and Dependents
•Dental & Vision: Company covers 50% of premiums for Employee and Dependents
•Voluntary Benefits: Life Insurance, FSA (Health and Dependent, Limited Purpose), HAS, and Gap Insurance
•Employee Assistant Program (EAP)
•401k - Traditional & Roth
•Life/AD&D and Long-Term Disability
•Tuition reimbursement
Equal Opportunity Policy Statement
Encore Semi, Inc. is an Equal Opportunity Employer that does not discriminate on the basis of actual or perceived race, religion, creed, color, age, sex, sexual orientation, gender, gender identity or expression, national origin, genetics, ancestry, marital status, civil union status, medical condition, disability (mental and physical), military and veteran status, pregnancy, childbirth and related medical conditions, or any other characteristic protected by applicable federal, state, or local laws and ordinances.
Encore Semi is also committed to compliance with all fair employment practices regarding citizenship and immigration status.
LinkedIn :: https://www.linkedin.com/in/rtl2gds/

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