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Locum Asic Rtl Design Engineer Jobs in Arizona (NOW HIRING)

... and ASIC/Foundry products.Partner closely with Architecture, Circuit Design, RTL Design ... Stakeholder EngagementCommunicate effectively with senior engineering leaders, product teams, and ...

Senior Digital Engineer

Chandler, AZ · On-site

$133K/yr

Work closely with Analog and Verification engineers to deliver high-quality silicon solutions ... SystemVerilog RTL for digital CMOS circuit design. * Strong understanding of ASIC design ...

Senior Digital Engineer

Chandler, AZ · On-site +1

$133K/yr

Work closely with Analog and Verification engineers to deliver high-quality silicon solutions ... SystemVerilog RTL for digital CMOS circuit design. * Strong understanding of ASIC design ...

Senior Digital Engineer

Chandler, AZ · On-site +1

$133K/yr

Work closely with Analog and Verification engineers to deliver high-quality silicon solutions ... SystemVerilog RTL for digital CMOS circuit design. * Strong understanding of ASIC design ...

Hardware Design Engineer

Tempe, AZ · On-site

$164K - $246K/yr

Develop, simulate, and verify FPGA RTL (using SystemVerilog, Verilog, or VHDL) for control, data ... Design high-speed interfaces (DDR4, SERDES, UART, I2C, SPI, LVDS) and perform signal/power ...

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Showing results 21-40

Locum Asic Rtl Design Engineer information

What is the difference between Locum Asic Rtl Design Engineer vs Contract Asic Rtl Design Engineer?

AspectLocum Asic Rtl Design EngineerContract Asic Rtl Design Engineer
CredentialsTypically requires relevant engineering degrees and RTL design experienceSimilar credentials, often with specific RTL design certifications
Work EnvironmentTemporary, short-term assignments often in multiple locationsProject-based roles, usually in a fixed location or remote
Employer UsageUsed by agencies or companies needing immediate, short-term expertiseEngaged by companies or staffing agencies for project-specific work

Both roles involve RTL design skills for ASIC development, but a Locum Asic Rtl Design Engineer typically fills short-term, temporary positions, often through staffing agencies, while a Contract Asic Rtl Design Engineer is engaged for specific projects with defined durations. The main difference lies in the nature and duration of employment, but both require similar technical credentials and work environments.

What are the most commonly searched types of Asic Rtl Design Engineer jobs in Arizona?

The most popular types of Asic Rtl Design Engineer jobs in Arizona are:

What job categories do people searching Locum Asic Rtl Design Engineer jobs in Arizona look for?

The top searched job categories for Locum Asic Rtl Design Engineer jobs in Arizona are:

What cities in Arizona are hiring for Locum Asic Rtl Design Engineer jobs?

Cities in Arizona with the most Locum Asic Rtl Design Engineer job openings:

Infographic showing various Locum Asic Rtl Design Engineer job openings in Arizona as of August 2026, with employment types broken down into 1% Internship, 85% Full Time, 9% Part Time, and 5% Contract. Highlights an 84% Physical, 5% Hybrid, and 11% Remote job distribution.

Advanced ASIC FPGA Engineer- (Sign-on Bonus Available)

General Dynamics Mission Systems, Inc

Scottsdale, AZ • On-site

$122K - $136K/yr

Full-time

Re-posted 9 days ago


General Dynamics Mission Systems rating

7.9

Company rating: 7.9 out of 10

Based on 30 frontline employees who took The Breakroom Quiz

128th of 244 rated software companies


Job description

Basic Qualifications
Bachelor's degree in Electrical or Computer Engineering, or a related Science, Engineering, Technology or Mathematics field. Also requires 5+ years of job-related experience, or a Master's degree and 3 years of job-related experience.
Clearance Requirements:
Department of Defense TS/SCI security clearance is preferred at time of hire. Candidates must be able to obtain a TS/SCI clearance within a reasonable amount of time from date of hire. Applicants selected will be subject to a U.S. Government security investigation and must meet eligibility requirements for access to classified information. Due to the nature of work performed within our facilities, U.S. citizenship is required.
Responsibilities for this Position
Duties and Tasks:
• Responsible for definition, design, verification and documentation for ASIC (Application Specific Integrated Circuit) and/or FPGA (Field Programmable Gate Array) developments
• Determines architecture, system simulation and detailed design approach
• Defines module interfaces and all aspects of device design and simulation
• Evaluates the process flow including but not limited to high level design, synthesis, place and route, timing and power utilization
• Creates test and simulation plans that establish functional criteria
• Verifies test results and analyzes performance
• May also review vendor capabilities, foundry technologies, device libraries and simulation tools
• Participates in the improvement of the ASIC/FPGA organizational processes
• Supports the generation of technical engineering products by using the appropriate standards, processes, procedures, and tools throughout the ASIC/FPGA development life cycle
• Contributes to the research and analysis of data, such as customer design proposal specifications, and manuals to determine feasibility of design or application
• Selects components and equipment based on analysis of specifications and reliability
• May provide leadership and/or direction to lower level employees
• Independently determines approach to solutions
• Contributes to the completion of major programs and projects
• Plans and executes project tasks for activities described above
Knowledge, Skills and Abilities:
• Proficient use and understanding of ASIC/FPGA engineering concepts, principles, and theories
• Proficient in the principles and techniques of ASIC/FPGA design
• Proficient understanding of ASIC/FPGA processes
• Proficient knowledge of other related disciplines
• Keeps abreast of technology trends
• Proficient awareness of business objectives and Engineering's role in achieving
• Proficient in Microsoft Office applications
• Proficient in ASIC/FPGA design tools
• Proficient written and verbal communications skills
• Ability to think creatively
• Ability to multi-task
• Proficient skill in communicating issues, impacts, and corrective actions
• Proficient ability to recognize and clearly report information relevant to sound ASIC/FPGA design
• Proficient ability to develop and sell concepts and ideas
• Regular contact with senior levels of internal work groups
• Works under limited direction
• Contact with project leaders and other professionals within the Engineering department and with project teams across the company
• Some contact with external customers
• Identifies opportunities to apply AI for continuous improvement and innovation
Key Responsibilities:
The individual will be responsible for and participate in the ASIC/FPGA product life cycle (requirements, design, implementation, and test). Must be knowledgeable in VHDL and/or Verilog RTL coding and be proficient in micro-architecture design. Successful candidates will have an understanding of digital design concepts and proficient in the digital design tool flow (synthesis, timing, place and route, and in system debug).
This candidate must have an ability to operate in a team environment and collaborate across the different teams as required to accomplish the design goals. Must have strong written and oral communication skills.
Basic Qualifications for Adv ASIC /FPGA Design Engineer:
  • Ability to generate micro architecture and detailed design approaches
  • Proficient in async design principals, timing closure, and constraint generation
  • Proficiency in HDL (VHDL/Verilog)
  • Proficiency in scripting languages such as Tcl, Python, or Perl
  • Effective communication, presentation skills, and high proficiency in technical problem solving
  • U.S. citizenship with the ability to obtain and maintain a Secret security clearance

Preferred Qualifications:
  • Leads technical tasks or small projects
  • Understanding of high reliability design principals
  • Experience with Xilinx and Microchip FPGAs along with associated tools (ISE, Vivado, Libero)
  • Experience with synthesis tools (Precision, Synplify)
  • Experience with verification tools (QuestaSim/UVM)
  • Experience with clock-domain-crossing tools (Questa CDC)
  • Experience with lab bring-up and debug (Oscilloscope, Logic Analyzer, ChipScope)
  • Active DoD Secret Clearance or higher

Workplace Options:
This position is fully on-site or hybrid/flex, as mutually agreed.
While on-site, you will be a part of the Scottsdale, AZ team. Learn more at https://gdmissionsystems.com/about-us/major-locations/scottsdale
Key Words: Verification, ASIC, FPGA, SystemVerilog, Verilog, Assertions (SVA), OVM, UVM, Digital Signal Processing (DSP), functional coverage, constrained random, formal verification, constrained random testing
#LI-Hybrid
#CJ1
Salary Note
This estimate represents the typical salary range for this position based on experience and other factors (geographic location, etc.). Actual pay may vary. This job posting will remain open until the position is filled.
Combined Salary Range
USD $122,785.00 - USD $136,215.00 /Yr.
Company Overview
General Dynamics Mission Systems (GDMS) engineers a diverse portfolio of high technology solutions, products and services that enable customers to successfully execute missions across all domains of operation. With a global team of 12,000+ top professionals, we partner with the best in industry to expand the bounds of innovation in the defense and scientific arenas. Given the nature of our work and who we are, we value trust, honesty, alignment and transparency. We offer highly competitive benefits and pride ourselves in being a great place to work with a shared sense of purpose. You will also enjoy a flexible work environment where contributions are recognized and rewarded. If who we are and what we do resonates with you, we invite you to join our high-performance team!
Equal Opportunity Employer / Individuals with Disabilities / Protected Veterans

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