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Google Asic Design Engineer Jobs in Arizona (NOW HIRING)

FPGA Engineer with Security Clearance

Tucson, AZ · On-site

$105K - $145K/yr

... • FPGA/ASIC design (VHDL coding) or FPGA/ASIC verification (SystemVerilog coding with UVM) • Xilinx or Microsemi devices and flow tools • Delivering FPGA/ASIC solutions to system level ...

Section Lead-Effector Digital Products

Tucson, AZ

$128K/yr

  • Medical

  • Dental

  • Vision

  • Life

  • Retirement

  • PTO

Typically requires a degree in Science, Technology, Engineering or Mathematics (STEM) and a minimum of 8 years of prior relevant experience * FPGA or ASIC design and/or verification * Integration and ...

New

Staff Digital Design Engineer

Chandler, AZ · On-site

$133K/yr

For over four decades, Cirrus Logic has been propelled by the top engineers in mixed-signal ... Exposure to low-power and high-performance ASIC design techniques. * Experience with back-end flows ...

Senior Digital Design Engineer

Chandler, AZ · On-site

$133K/yr

For over four decades, Cirrus Logic has been propelled by the top engineers in mixed-signal ... Exposure to low-power and high-performance ASIC design techniques. * Experience with back-end flows ...

Section Lead-Effector Digital Products

Tucson, AZ

$128K/yr

  • Medical

  • Dental

  • Vision

  • Life

  • Retirement

  • PTO

Typically requires a degree in Science, Technology, Engineering or Mathematics (STEM) and a minimum of 8 years of prior relevant experience * FPGA or ASIC design and/or verification * Integration and ...

New

Section Lead-Effector Digital Products

Phoenix, AZ

$135K/yr

  • Medical

  • Dental

  • Vision

  • Life

  • Retirement

  • PTO

Typically requires a degree in Science, Technology, Engineering or Mathematics (STEM) and a minimum of 8 years of prior relevant experience * FPGA or ASIC design and/or verification * Integration and ...

New

Showing results 21-40

Google Asic Design Engineer information

See Arizona salary details

$87.6K

$140K

$188.2K

How much do google asic design engineer jobs pay per year?

As of Aug 16, 2026, the average yearly pay for google asic design engineer in Arizona is $139,965.00, according to ZipRecruiter salary data. Most workers in this role earn between $122,500.00 and $167,700.00 per year, depending on experience, location, and employer.

What does a Google ASIC Design Engineer do?

A Google ASIC Design Engineer is responsible for designing and developing custom integrated circuits, known as Application-Specific Integrated Circuits (ASICs), that power Google's data centers, cloud infrastructure, and consumer devices. Their work involves collaborating with cross-functional teams to define requirements, create architecture, perform logic and physical design, and validate the silicon before production. They use advanced design tools and methodologies to ensure high performance, low power consumption, and reliability. Ultimately, their contributions help improve the efficiency and capabilities of Google's hardware products.

How does a Google ASIC Design Engineer typically collaborate with cross-functional teams during the chip development process?

As a Google ASIC Design Engineer, you will work closely with teams such as architecture, verification, software, and hardware validation to ensure successful chip delivery. Collaboration often involves regular meetings to align on design specifications, resolve integration issues, and discuss performance optimization. Effective communication is essential, as you’ll need to translate requirements from system architects into detailed hardware designs and provide feedback to verification and validation teams. This cross-functional interaction fosters a dynamic work environment and helps ensure the final product meets Google's rigorous standards.

What are the key skills and qualifications needed to thrive as a Google ASIC Design Engineer, and why are they important?

To thrive as a Google ASIC Design Engineer, you need a strong background in electrical engineering, digital logic design, and experience with ASIC development, typically backed by a relevant degree. Familiarity with hardware description languages (such as Verilog or VHDL), EDA tools (like Synopsys or Cadence), and an understanding of SoC architectures are essential, and related certifications can be valuable. Strong problem-solving skills, attention to detail, and effective teamwork and communication abilities help set candidates apart. These skills are crucial for designing reliable, high-performance ASICs that meet Google's specifications and project timelines.

What is the difference between Google Asic Design Engineer vs Google FPGA Design Engineer?

AspectGoogle Asic Design EngineerGoogle FPGA Design Engineer
Required CredentialsBachelor's/Master's in Electrical Engineering or Computer Engineering; experience in ASIC designBachelor's/Master's in Electrical Engineering or Computer Engineering; FPGA design experience
Work EnvironmentDesigning custom silicon chips for Google productsDeveloping and testing FPGA prototypes for hardware acceleration
Employer & Industry UsagePrimarily in semiconductor and hardware design teams at GoogleHardware prototyping and acceleration teams at Google

The main difference between a Google Asic Design Engineer and a Google FPGA Design Engineer lies in their focus: ASIC engineers design custom chips for optimized performance, while FPGA engineers develop flexible hardware prototypes using field-programmable gate arrays. Both roles require strong electrical engineering skills but serve different stages of hardware development.

What job categories do people searching Google Asic Design Engineer jobs in Arizona look for?

The top searched job categories for Google Asic Design Engineer jobs in Arizona are:

What cities in Arizona are hiring for Google Asic Design Engineer jobs?

Cities in Arizona with the most Google Asic Design Engineer job openings:

Infographic showing various Google Asic Design Engineer job openings in Arizona as of August 2026, with employment types broken down into 6% As Needed, 72% Full Time, and 22% Contract. Highlights an 94% In-person, and 6% Remote job distribution, with an average salary of $139,965 per year, or $67.3 per hour.

Advanced ASIC FPGA Engineer- (Sign-on Bonus Available)

General Dynamics Mission Systems, Inc

Scottsdale, AZ • On-site

$122K - $136K/yr

Full-time

Re-posted 9 days ago


General Dynamics Mission Systems rating

7.9

Company rating: 7.9 out of 10

Based on 30 frontline employees who took The Breakroom Quiz

128th of 244 rated software companies


Job description

Basic Qualifications
Bachelor's degree in Electrical or Computer Engineering, or a related Science, Engineering, Technology or Mathematics field. Also requires 5+ years of job-related experience, or a Master's degree and 3 years of job-related experience.
Clearance Requirements:
Department of Defense TS/SCI security clearance is preferred at time of hire. Candidates must be able to obtain a TS/SCI clearance within a reasonable amount of time from date of hire. Applicants selected will be subject to a U.S. Government security investigation and must meet eligibility requirements for access to classified information. Due to the nature of work performed within our facilities, U.S. citizenship is required.
Responsibilities for this Position
Duties and Tasks:
• Responsible for definition, design, verification and documentation for ASIC (Application Specific Integrated Circuit) and/or FPGA (Field Programmable Gate Array) developments
• Determines architecture, system simulation and detailed design approach
• Defines module interfaces and all aspects of device design and simulation
• Evaluates the process flow including but not limited to high level design, synthesis, place and route, timing and power utilization
• Creates test and simulation plans that establish functional criteria
• Verifies test results and analyzes performance
• May also review vendor capabilities, foundry technologies, device libraries and simulation tools
• Participates in the improvement of the ASIC/FPGA organizational processes
• Supports the generation of technical engineering products by using the appropriate standards, processes, procedures, and tools throughout the ASIC/FPGA development life cycle
• Contributes to the research and analysis of data, such as customer design proposal specifications, and manuals to determine feasibility of design or application
• Selects components and equipment based on analysis of specifications and reliability
• May provide leadership and/or direction to lower level employees
• Independently determines approach to solutions
• Contributes to the completion of major programs and projects
• Plans and executes project tasks for activities described above
Knowledge, Skills and Abilities:
• Proficient use and understanding of ASIC/FPGA engineering concepts, principles, and theories
• Proficient in the principles and techniques of ASIC/FPGA design
• Proficient understanding of ASIC/FPGA processes
• Proficient knowledge of other related disciplines
• Keeps abreast of technology trends
• Proficient awareness of business objectives and Engineering's role in achieving
• Proficient in Microsoft Office applications
• Proficient in ASIC/FPGA design tools
• Proficient written and verbal communications skills
• Ability to think creatively
• Ability to multi-task
• Proficient skill in communicating issues, impacts, and corrective actions
• Proficient ability to recognize and clearly report information relevant to sound ASIC/FPGA design
• Proficient ability to develop and sell concepts and ideas
• Regular contact with senior levels of internal work groups
• Works under limited direction
• Contact with project leaders and other professionals within the Engineering department and with project teams across the company
• Some contact with external customers
• Identifies opportunities to apply AI for continuous improvement and innovation
Key Responsibilities:
The individual will be responsible for and participate in the ASIC/FPGA product life cycle (requirements, design, implementation, and test). Must be knowledgeable in VHDL and/or Verilog RTL coding and be proficient in micro-architecture design. Successful candidates will have an understanding of digital design concepts and proficient in the digital design tool flow (synthesis, timing, place and route, and in system debug).
This candidate must have an ability to operate in a team environment and collaborate across the different teams as required to accomplish the design goals. Must have strong written and oral communication skills.
Basic Qualifications for Adv ASIC /FPGA Design Engineer:
  • Ability to generate micro architecture and detailed design approaches
  • Proficient in async design principals, timing closure, and constraint generation
  • Proficiency in HDL (VHDL/Verilog)
  • Proficiency in scripting languages such as Tcl, Python, or Perl
  • Effective communication, presentation skills, and high proficiency in technical problem solving
  • U.S. citizenship with the ability to obtain and maintain a Secret security clearance

Preferred Qualifications:
  • Leads technical tasks or small projects
  • Understanding of high reliability design principals
  • Experience with Xilinx and Microchip FPGAs along with associated tools (ISE, Vivado, Libero)
  • Experience with synthesis tools (Precision, Synplify)
  • Experience with verification tools (QuestaSim/UVM)
  • Experience with clock-domain-crossing tools (Questa CDC)
  • Experience with lab bring-up and debug (Oscilloscope, Logic Analyzer, ChipScope)
  • Active DoD Secret Clearance or higher

Workplace Options:
This position is fully on-site or hybrid/flex, as mutually agreed.
While on-site, you will be a part of the Scottsdale, AZ team. Learn more at https://gdmissionsystems.com/about-us/major-locations/scottsdale
Key Words: Verification, ASIC, FPGA, SystemVerilog, Verilog, Assertions (SVA), OVM, UVM, Digital Signal Processing (DSP), functional coverage, constrained random, formal verification, constrained random testing
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Salary Note
This estimate represents the typical salary range for this position based on experience and other factors (geographic location, etc.). Actual pay may vary. This job posting will remain open until the position is filled.
Combined Salary Range
USD $122,785.00 - USD $136,215.00 /Yr.
Company Overview
General Dynamics Mission Systems (GDMS) engineers a diverse portfolio of high technology solutions, products and services that enable customers to successfully execute missions across all domains of operation. With a global team of 12,000+ top professionals, we partner with the best in industry to expand the bounds of innovation in the defense and scientific arenas. Given the nature of our work and who we are, we value trust, honesty, alignment and transparency. We offer highly competitive benefits and pride ourselves in being a great place to work with a shared sense of purpose. You will also enjoy a flexible work environment where contributions are recognized and rewarded. If who we are and what we do resonates with you, we invite you to join our high-performance team!
Equal Opportunity Employer / Individuals with Disabilities / Protected Veterans

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