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Serdes Jobs in Arizona (NOW HIRING)

Intel

Principal SerDes Architect

Phoenix, AZ · On-site

$220K - $311K/yr

Preferred Qualifications - Proven track record of technical leadership in analog circuit design, influencing direction across organizations or the industry. - Familiarity with SerDes fundamentals ...

Intel

Principal Engineer, AMS IP Architecture

Phoenix, AZ · On-site

$220K - $311K/yr

Key Responsibilities SerDes Modeling: Architected end-to-end PCIe SerDes models (NRZ/PAM4) in MATLAB/Simulink, capturing complex TX/RX equalization behavior. Sign-Off Compliance: Executed 128Gbps ...

Intel Corporation

Senior Analog Design Engineer

Phoenix, AZ · On-site

$200K/yr

Minimum Qualifications Bachelor's degree in Electrical Engineering, Electronics Engineering, or a related field. 6+ years of experience in analog/mixed-signal circuit design for high-speed SerDes or ...

Viasat, Inc.

Hardware Engineer (Space)

Tempe, AZ · On-site

$164K - $246K/yr

Design high-speed digital interfaces including DDR4, SERDES, UART, and SPI * Perform HyperLynx power/signal integrity analysis and implement corrective design changes * Conduct worst case analysis ...

Viasat, Inc.

Hardware Engineer (Space)

Tempe, AZ · On-site

$193K - $290K/yr

Design high-speed digital interfaces including DDR4, SERDES, UART, and SPI * Perform HyperLynx power/signal integrity analysis and implement corrective design changes * Conduct worst case analysis ...

Viasat, Inc.

Hardware Engineer (Space)

Tempe, AZ · On-site

$193K - $290K/yr

Design high-speed digital interfaces including DDR4, SERDES, UART, and SPI * Perform HyperLynx power/signal integrity analysis and implement corrective design changes * Conduct worst case analysis ...

Intel

Senior Analog Design Engineer

Phoenix, AZ · On-site

$200K/yr

Minimum Qualifications Bachelor's degree in Electrical Engineering, Electronics Engineering, or a related field. 6+ years of experience in analog/mixed-signal circuit design for high-speed SerDes or ...

Viasat, Inc.

Hardware Engineer (Space)

Tempe, AZ · On-site

$193K - $290K/yr

Design high-speed digital interfaces including DDR4, SERDES, UART, and SPI * Perform HyperLynx power/signal integrity analysis and implement corrective design changes * Conduct worst case analysis ...

Viasat

Hardware Engineer (Space)

Tempe, AZ · On-site

$132.50 - $209.50/hr

Design high‑speed digital interfaces including DDR4, SERDES, UART, and SPI * Perform HyperLynx power/signal integrity analysis and implement corrective design changes * Conduct worst case analysis ...

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$131.7K

$270.7K

How much do serdes jobs pay per year?

As of Aug 18, 2026, the average yearly pay for serdes in Arizona is $131,723.00, according to ZipRecruiter salary data. Most workers in this role earn between $88,500.00 and $147,200.00 per year, depending on experience, location, and employer.

What is a SerDes engineer?

SerDes engineers are professionals who design, develop, and test Serializer/Deserializer (SerDes) circuits and systems. SerDes technology is used to convert data between serial and parallel interfaces, enabling high-speed data transmission in electronics such as computer motherboards, network devices, and integrated circuits. These engineers work on optimizing signal integrity, reducing power consumption, and ensuring reliable data transfer over high-speed links. Their expertise is critical in industries like telecommunications, data centers, and consumer electronics.

What are the key skills and qualifications needed to thrive as a SerDes engineer?

To thrive as a SerDes Engineer, you need strong expertise in high-speed digital and analog circuit design, signal integrity, and a degree in electrical or electronics engineering. Familiarity with EDA tools like Cadence or Synopsys, experience in simulation software, and knowledge of relevant standards (e.g., PCIe, USB, Ethernet) are typically required. Excellent problem-solving abilities, attention to detail, and effective teamwork make someone stand out in this role. These skills are crucial for ensuring robust, high-performance serial communication interfaces in advanced electronic systems.

What are some common challenges faced by SerDes engineers during high-speed interface design projects?

SerDes engineers often encounter challenges related to signal integrity, such as minimizing jitter and crosstalk when working with high-speed data transmission. Achieving reliable performance requires careful PCB layout, selection of appropriate materials, and thorough simulation and validation. Additionally, SerDes engineers must frequently collaborate with hardware, firmware, and verification teams to ensure seamless integration and compliance with industry standards like PCIe or Ethernet. Staying updated with rapidly evolving protocols and troubleshooting interoperability issues are also common aspects of the role.

What is the difference between Serdes vs Network Engineer?

AspectSerdesNetwork Engineer
Required CredentialsTypically certifications in electronics, FPGA, or hardware designNetworking certifications like CCNA, CCNP, or CompTIA Network+
Work EnvironmentHardware labs, manufacturing facilities, R&D centersOffice settings, data centers, client sites
Industry UsageTelecommunications, data communications, hardware manufacturingIT, telecommunications, enterprise networks

Serdes (Serializer/Deserializer) specialists focus on hardware design and signal integrity in communication systems, while Network Engineers manage network infrastructure and connectivity. Both roles require technical expertise but differ in their focus areas and work environments. Understanding these differences helps in choosing the right career path or job search focus.

What are the most commonly searched types of Serdes jobs in Arizona?

The most popular types of Serdes jobs in Arizona are:

What are popular job titles related to Serdes jobs in Arizona?

For Serdes jobs in Arizona, the most frequently searched job titles are:

What job categories do people searching Serdes jobs in Arizona look for?

The top searched job categories for Serdes jobs in Arizona are:

What cities in Arizona are hiring for Serdes jobs?

Cities in Arizona with the most Serdes job openings:

Serdes jobs near you
Infographic showing various Serdes job openings in Arizona as of August 2026, with employment types broken down into 84% Full Time, and 16% Contract. Highlights an 84% In-person, and 16% Remote job distribution, with an average salary of $131,723 per year, or $63.3 per hour.

Principal Analog Circuit Design Engineer - SerDes

Intel

Phoenix, AZ • On-site

$200K/yr

Full-time

Medical, Retirement, PTO

Re-posted 19 days ago

Intel rating

8.7

Company rating: 8.7 out of 10

Based on 147 frontline employees who took The Breakroom Quiz

19th of 159 rated electronics manufacturers

Job description

Job Details:Job Description: 

We are seeking a highly experienced and motivated Principal Analog Design Engineer to lead the design and validation of cutting-edge analog circuits for high-speed (112G and 224G) SerDes applications. In this role, you will be a key technical driver in the definition, execution, and validation of complex analog and mixed-signal designs.

This role involves providing technical direction and mentorship to layout and less experienced analog design engineers, fostering a collaborative and knowledge-sharing culture. You will engage closely with cross-functional teams, including systems, digital design, and test engineering, to ensure robust design implementation and validation.Strong problem-solving skills, analytical thinking, and a commitment to execution excellence are essential. As a principal-level engineer, you will be expected to demonstrate a proven track record of delivering high-quality results in advanced FinFET CMOS technology within high-speed SerDes design environments. Excellent documentation and presentation skills are also required to clearly communicate complex design concepts and results.

The ideal candidate is self-driven, detail-oriented, and thrives in a fast-paced environment. You will actively participate in technical discussions across multiple disciplines, including analog/mixed-signal design, post-silicon validation, and system-level collaboration.

Desired traits:

Excellent communication, documentation, and presentation skills.

Strong problem-solving attitude and ability to deliver under tight schedules in a collaborative environment.

Demonstrated leadership in cross-functional technical discussions and decision-making.

Team player with a collaborative mindset, willingness to share knowledge, and a hands-on approach to problem-solving

Qualifications:

Minimum Qualifications

Master's degree in Electrical Engineering, Electronics Engineering, or related field.

8+ years of experience in analog/mixed-signal circuit design for high-speed SerDes applications. Proven expertise in one or more of the following areas: PLL, CDR, CTLE, DFE, ADC, or Transmitter (TX) design.

Strong understanding of high-speed communication standards such as PCIe (Gen5/Gen6) and Ethernet (100G/400G/800G).

Solid foundational knowledge of analog design principles-noise, jitter, matching, stability, and linearity.

Hands-on experience with advanced FinFET CMOS process technologies (7nm or below).

Proficiency in analog design and simulation tools such as Cadence Virtuoso/ADE, HSPICE, or equivalent.

Experience in silicon bring-up, post-silicon validation, and lab debug of analog circuits.

Preferred Qualifications

Ph.D. in Electrical Engineering, Electronics Engineering, or related field.

10+ years of experience in analog design for high-speed SerDes (56G/112G/224G) applications.

Deep expertise in transmitter and receiver architecture, CDR loops, equalization techniques, and advanced ADC architectures.

Familiarity with next-generation standards such as PCIe 6.0+, 800G/1.6T Ethernet, JESD, and other SerDes protocols.

Hands-on experience in behavioral modeling (Verilog-A), MATLAB-based analysis, and automation scripting (Python/Tcl/Perl).

Strong understanding of signal integrity, channel modeling, and system-level link performance.

Proven ability to mentor junior engineers, guide layout implementation, and drive design reviews..

Job Type:Experienced HireShift:Shift 1 (United States of America)Primary Location: US, California, Santa ClaraAdditional Locations:US, Arizona, Phoenix, US, Oregon, HillsboroBusiness group:The Central Engineering Group (CEG) is Intel's data-driven organization that builds scalable engineering solutions across three pillars: Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom silicon), and Foundry Enablement (supporting top customers and validating technologies). The team focuses on customer-driven, end-to-end solutions with short development cycles to deliver measurable business impact across Intel's product and foundry businesses.Posting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of TrustThis role is a Position of Trust. Should you accept this position, you must consent to and pass an extended Background Investigation, which includes (subject to country law), extended education, SEC sanctions, and additional criminal and civil checks. For internals, this investigation may or may not be completed prior to starting the position. For additional questions, please contact your Recruiter.Benefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.

Annual Salary Range for jobs which could be performed in the US: $220,920.00-311,890.00 USDThe range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

*

ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.

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About Intel

Sourced by ZipRecruiter

Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore's Law to bring smart, connected devices to every person on Earth

Industry

Manufacturing

Company size

10,000+ Employees

Headquarters location

Santa Clara, CA, US

Year founded

1968

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