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Serdes Jobs in Arizona (NOW HIRING)

Intel

Principal SerDes Architect

Phoenix, AZ

$220K - $311K/yr

Preferred Qualifications - Proven track record of technical leadership in analog circuit design, influencing direction across organizations or the industry. - Familiarity with SerDes fundamentals ...

Viasat, Inc.

Hardware Engineer (Space)

Tempe, AZ · On-site

$164K - $246K/yr

Design high-speed digital interfaces including DDR4, SERDES, UART, and SPI * Perform HyperLynx power/signal integrity analysis and implement corrective design changes * Conduct worst case analysis ...

Viasat, Inc.

Hardware Engineer (Space)

Tempe, AZ · On-site

$164K - $246K/yr

Design high-speed digital interfaces including DDR4, SERDES, UART, and SPI * Perform HyperLynx power/signal integrity analysis and implement corrective design changes * Conduct worst case analysis ...

Viasat

Hardware Engineer (Space)

Tempe, AZ · On-site

$150 - $200/hr

Design high-speed digital interfaces including DDR4, SERDES, UART, and SPI * Perform HyperLynx power/signal integrity analysis and implement corrective design changes * Conduct worst case analysis ...

Moog Inc

Staff Digital Systems Engineer

Gilbert, AZ · On-site

$150 - $200/hr

Design, integrate, and verify high-speed digital interfaces such as DDR, PCIe, Ethernet, SerDes, LVDS, SPI, I2C, or similar technologies. * Support board bring‑up, hardware integration, debug, and ...

Intel

Director, Engineering

Phoenix, AZ

Demonstrated success delivering high-speed PHY, SerDes, DDR, LPDDR, or other complex mixed-signal IPs into production.Deep expertise in advanced node implementation including Intel 18A, Intel 14A ...

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See Arizona salary details

$75K

$131.7K

$270.7K

How much do serdes jobs pay per year?

As of Sep 7, 2026, the average yearly pay for serdes in Arizona is $131,723.00, according to ZipRecruiter salary data. Most workers in this role earn between $88,500.00 and $147,200.00 per year, depending on experience, location, and employer.

What is a SerDes engineer?

SerDes engineers are professionals who design, develop, and test Serializer/Deserializer (SerDes) circuits and systems. SerDes technology is used to convert data between serial and parallel interfaces, enabling high-speed data transmission in electronics such as computer motherboards, network devices, and integrated circuits. These engineers work on optimizing signal integrity, reducing power consumption, and ensuring reliable data transfer over high-speed links. Their expertise is critical in industries like telecommunications, data centers, and consumer electronics.

What are the key skills and qualifications needed to thrive as a SerDes engineer?

To thrive as a SerDes Engineer, you need strong expertise in high-speed digital and analog circuit design, signal integrity, and a degree in electrical or electronics engineering. Familiarity with EDA tools like Cadence or Synopsys, experience in simulation software, and knowledge of relevant standards (e.g., PCIe, USB, Ethernet) are typically required. Excellent problem-solving abilities, attention to detail, and effective teamwork make someone stand out in this role. These skills are crucial for ensuring robust, high-performance serial communication interfaces in advanced electronic systems.

What are some common challenges faced by SerDes engineers during high-speed interface design projects?

SerDes engineers often encounter challenges related to signal integrity, such as minimizing jitter and crosstalk when working with high-speed data transmission. Achieving reliable performance requires careful PCB layout, selection of appropriate materials, and thorough simulation and validation. Additionally, SerDes engineers must frequently collaborate with hardware, firmware, and verification teams to ensure seamless integration and compliance with industry standards like PCIe or Ethernet. Staying updated with rapidly evolving protocols and troubleshooting interoperability issues are also common aspects of the role.

What is the difference between Serdes vs Network Engineer?

AspectSerdesNetwork Engineer
Required CredentialsTypically certifications in electronics, FPGA, or hardware designNetworking certifications like CCNA, CCNP, or CompTIA Network+
Work EnvironmentHardware labs, manufacturing facilities, R&D centersOffice settings, data centers, client sites
Industry UsageTelecommunications, data communications, hardware manufacturingIT, telecommunications, enterprise networks

Serdes (Serializer/Deserializer) specialists focus on hardware design and signal integrity in communication systems, while Network Engineers manage network infrastructure and connectivity. Both roles require technical expertise but differ in their focus areas and work environments. Understanding these differences helps in choosing the right career path or job search focus.

What are the most commonly searched types of Serdes jobs in Arizona?

The most popular types of Serdes jobs in Arizona are:

What are popular job titles related to Serdes jobs in Arizona?

For Serdes jobs in Arizona, the most frequently searched job titles are:

What job categories do people searching Serdes jobs in Arizona look for?

The top searched job categories for Serdes jobs in Arizona are:

What cities in Arizona are hiring for Serdes jobs?

Cities in Arizona with the most Serdes job openings:

Serdes jobs near you
Infographic showing various Serdes job openings in Arizona as of August 2026, with employment types broken down into 84% Full Time, and 16% Contract. Highlights an 84% In-person, and 16% Remote job distribution, with an average salary of $131,723 per year, or $63.3 per hour.

Principal SerDes Architect

Intel

Phoenix, AZ

$220K - $311K/yr

Full-time

Medical, Retirement, PTO

Re-posted 11 days ago

Key responsibilities

  • Lead architecture definition and development of next-generation high-speed IO PHYs with industry-leading PPA metrics

  • Design, develop, and optimize analog circuits, including TX/RX blocks, in advanced process nodes for analog and mixed-signal IPs

  • Create floorplans, extract chip parameters, simulate analog behavior models, and verify designs against specifications

Intel rating

8.7

Company rating: 8.7 out of 10

Based on 147 frontline employees who took The Breakroom Quiz

18th of 161 rated electronics manufacturers

Job description

Job Details:Job Description: 

The Role and Impact
As a Principal Engineer in Analog Circuit Design, you will be at the forefront of innovation, driving technical excellence and advancing Intel's leadership in analog and mixed-signal IPs. This role is pivotal in defining and delivering cutting-edge designs in advanced process nodes, ensuring optimal performance, power efficiency, and robustness. As a recognized domain expert, you will influence technical direction across Intel and the broader industry while mentoring other technical leaders and fostering a community of innovation.
Key Responsibilities

- Lead architecture definition and development of next-generation high-speed IO PHYs with industry-leading PPA metrics

- Design, develop, and optimize analog circuits, including TX/RX blocks, in advanced process nodes for analog and mixed-signal IPs.
- Create floorplans, extract chip parameters, and simulate analog behavior models to meet performance, power, and area goals.
- Develop comprehensive test plans, verify designs against microarchitecture specifications, and evaluate test results to ensure optimal functionality.
- Optimize circuit performance, power, area, and yield, identifying and resolving design challenges.
- Collaborate with architecture and layout teams to design robust circuits with best-in-class electrical capabilities.
- Provide technical leadership across Intel and the industry by developing technical strategies and aligning them with organizational goals.
- Act as a mentor and role model for other technical leaders, fostering growth, providing guidance, and cultivating a community of technical excellence.
- Serve as a change agent by driving innovation, relentless execution, and delivering leadership solutions to market.

Qualifications:

Minimum Qualifications
- Bachelor's or BS degree in Electrical Engineering, Computer Engineering, or a related field, and 12 or more years of experience in analog circuit design. Alternatively, a Master's degree with 10 or more years of experience.
- Deep expertise in analog circuit design fundamentals, including TX/RX blocks, I/O PHY architecture , low-power design, and signal and power integrity.
- Proficiency in analog behavior modeling, circuit simulation, and optimization techniques for power, performance, area, and yield.
- Demonstrated experience in advanced process nodes and the ability to address challenges in analog and mixed-signal design.
Preferred Qualifications
- Proven track record of technical leadership in analog circuit design, influencing direction across organizations or the industry.

- Familiarity with SerDes fundamentals

- Familiarity with UCIe and PCIe specifications
- Strong understanding of analog architecture, layout optimization, and best practices in analog circuit robustness and electrical capabilities.
- Excellent strategic thinking and problem-solving skills, with the ability to align technical vision with organizational goals.
- Experience mentoring and developing technical talent, fostering collaboration, and driving innovation across teams.


Join Intel and be part of a team that is shaping the future of technology. If you are ready to lead, innovate, and make a difference, we encourage you to apply today.

Job Type:Experienced HireShift:Shift 1 (United States of America)Primary Location: US, California, Santa ClaraAdditional Locations:US, Arizona, Phoenix, US, California, Folsom, US, Oregon, HillsboroPosting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of TrustThis role is a Position of Trust. Should you accept this position, you must consent to and pass an extended Background Investigation, which includes (subject to country law), extended education, SEC sanctions, and additional criminal and civil checks. For internals, this investigation may or may not be completed prior to starting the position. For additional questions, please contact your Recruiter.Benefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.

Annual Salary Range for jobs which could be performed in the US: $220,920.00-311,890.00 USDThe range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

*

ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.

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About Intel

Sourced by ZipRecruiter

Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore's Law to bring smart, connected devices to every person on Earth

Industry

Manufacturing

Company size

10,000+ Employees

Headquarters location

Santa Clara, CA, US

Year founded

1968

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