RF SoC Design Engineer
Tempe, AZ ยท On-site
Help guide chip design for proper system timing and synchronization of the interactions between system components such as PLL, DAC, ADC, and on-chip digital post-processing of ADC outputs. Digital ...
Tempe, AZ ยท On-site
Help guide chip design for proper system timing and synchronization of the interactions between system components such as PLL, DAC, ADC, and on-chip digital post-processing of ADC outputs. Digital ...
Tempe, AZ ยท On-site
Help guide chip design for proper system timing and synchronization of the interactions between system components such as PLL, DAC, ADC, and on-chip digital post-processing of ADC outputs. Digital ...
Arizona, LA ยท On-site
Help guide chip design for proper system timing and synchronization of the interactions between system components such as PLL, DAC, ADC, and on-chip digital post-processing of ADC outputs. Digital ...
Arizona, LA ยท On-site
Help guide chip design for proper system timing and synchronization of the interactions between system components such as PLL, DAC, ADC, and on-chip digital post-processing of ADC outputs. Digital ...
Phoenix, AZ ยท On-site
$128K - $153K/yr
Hands-on experience in advanced node test chip design and scribe line optimization for 3nm-16nm FinFETs and sub 3nm GAA FETs, Backside power delivery * Understanding of Physical Design flows for ...
Phoenix, AZ ยท On-site
$128K - $153K/yr
Hands-on experience in advanced node test chip design and scribe line optimization for 3nm-16nm FinFETs and sub 3nm GAA FETs, Backside power delivery * Understanding of Physical Design flows for ...
Phoenix, AZ ยท On-site
$135K - $139K/yr
Physical Design Develop & own physical design implementation of multi-hierarchy low-power designs ... Exp. in Block-level & Full-chip floor-planning & power grid planning,w/Python, TCL,or Perl progr ...
Phoenix, AZ ยท On-site
$135K - $139K/yr
Physical Design Develop & own physical design implementation of multi-hierarchy low-power designs ... Exp. in Block-level & Full-chip floor-planning & power grid planning,w/Python, TCL,or Perl progr ...
Phoenix, AZ ยท On-site
$164K - $311K/yr
Work closely with the clocking team and full-chip designers to balance timing fixes, power delivery, clocking, and partitioning. * Collaborate with architecture, clocking design, DFT and logic design ...
Phoenix, AZ ยท On-site
$164K - $311K/yr
Work closely with the clocking team and full-chip designers to balance timing fixes, power delivery, clocking, and partitioning. * Collaborate with architecture, clocking design, DFT and logic design ...
$164K - $311K/yr
Work closely with the clocking team and full-chip designers to balance timing fixes, power delivery, clocking, and partitioning. * Collaborate with architecture, clocking design, DFT and logic design ...
$164K - $311K/yr
Work closely with the clocking team and full-chip designers to balance timing fixes, power delivery, clocking, and partitioning. * Collaborate with architecture, clocking design, DFT and logic design ...
Tempe, AZ ยท On-site
$176K - $264K/yr
Architecting Design Verification environments for ASICs and FPGAs ... Working with RTL, System and software engineers to determine appropriate coverage closure for chip ...
Tempe, AZ ยท On-site
$176K - $264K/yr
Architecting Design Verification environments for ASICs and FPGAs ... Working with RTL, System and software engineers to determine appropriate coverage closure for chip ...
Chandler, AZ ยท On-site
$133K - $163K/yr
You will be responsible for end-to-end functional verification across block-level and chip-level ... Design and implement UVM-based testbenches, including infrastructure, scoreboards, checkers, and ...
Chandler, AZ ยท On-site
$133K - $163K/yr
You will be responsible for end-to-end functional verification across block-level and chip-level ... Design and implement UVM-based testbenches, including infrastructure, scoreboards, checkers, and ...
Chandler, AZ ยท On-site
$133K - $163K/yr
You will be responsible for end-to-end functional verification across block-level and chip-level ... Design and implement UVM-based testbenches, including infrastructure, scoreboards, checkers, and ...
Chandler, AZ ยท On-site
$133K - $163K/yr
You will be responsible for end-to-end functional verification across block-level and chip-level ... Design and implement UVM-based testbenches, including infrastructure, scoreboards, checkers, and ...
Chandler, AZ ยท On-site
$133K - $163K/yr
You will be responsible for end-to-end functional verification across block-level and chip-level ... Design and implement UVM-based testbenches, including infrastructure, scoreboards, checkers, and ...
Chandler, AZ ยท On-site
$133K - $163K/yr
You will be responsible for end-to-end functional verification across block-level and chip-level ... Design and implement UVM-based testbenches, including infrastructure, scoreboards, checkers, and ...
Tempe, AZ ยท On-site
$176K - $264K/yr
Architecting Design Verification environments for ASICs and FPGAs ... Working with RTL, System and software engineers to determine appropriate coverage closure for chip ...
Tempe, AZ ยท On-site
$176K - $264K/yr
Architecting Design Verification environments for ASICs and FPGAs ... Working with RTL, System and software engineers to determine appropriate coverage closure for chip ...
$122K - $232K/yr
Full chip physical design completion and verification for tapein/tapeout Preferred Qualifications: * Experience optimizing designs for signal integrity and power integrity * Experience in chip-level ...
$122K - $232K/yr
Full chip physical design completion and verification for tapein/tapeout Preferred Qualifications: * Experience optimizing designs for signal integrity and power integrity * Experience in chip-level ...
Phoenix, AZ ยท On-site
$122K - $232K/yr
Full chip physical design completion and verification for tapein/tapeout Preferred Qualifications: * Experience optimizing designs for signal integrity and power integrity * Experience in chip-level ...
Phoenix, AZ ยท On-site
$122K - $232K/yr
Full chip physical design completion and verification for tapein/tapeout Preferred Qualifications: * Experience optimizing designs for signal integrity and power integrity * Experience in chip-level ...
Chandler, AZ ยท On-site
$114K - $166K/yr
Function as the chip lead and lead analog or digital designer for projects and perform chip floor ... Document and present design and evaluation review documentation for peer review or before ...
Chandler, AZ ยท On-site
$114K - $166K/yr
Function as the chip lead and lead analog or digital designer for projects and perform chip floor ... Document and present design and evaluation review documentation for peer review or before ...
Chandler, AZ ยท On-site
$133K - $163K/yr
You will be responsible for end-to-end functional verification across block-level and chip-level ... Design and implement UVM-based testbenches, including infrastructure, scoreboards, checkers, and ...
Chandler, AZ ยท On-site
$133K - $163K/yr
You will be responsible for end-to-end functional verification across block-level and chip-level ... Design and implement UVM-based testbenches, including infrastructure, scoreboards, checkers, and ...
Chip layout experience for protection devices is desirable * Experience with Cadence environment ... Design, layout and verification of protection and small signal products to meet the specifications ...
Chip layout experience for protection devices is desirable * Experience with Cadence environment ... Design, layout and verification of protection and small signal products to meet the specifications ...
Scottsdale, AZ ยท On-site
As a Principal Design Engineer located in Scottsdale, Arizona, you will have the opportunity to ... Chip layout experience for protection devices is desirable * Experience with Cadence environment ...
Scottsdale, AZ ยท On-site
As a Principal Design Engineer located in Scottsdale, Arizona, you will have the opportunity to ... Chip layout experience for protection devices is desirable * Experience with Cadence environment ...
Chandler, AZ ยท On-site
$198K/yr
Analog Design Engineer Job Responsibility: * Design high-performance analog and mixed-signal ... Translate chip-level requirements(data rate, BER, Jitter budget) into detailed block level ...
Chandler, AZ ยท On-site
$198K/yr
Analog Design Engineer Job Responsibility: * Design high-performance analog and mixed-signal ... Translate chip-level requirements(data rate, BER, Jitter budget) into detailed block level ...
Chandler, AZ ยท On-site
$198K/yr
Analog Design Engineer Job Responsibility: * Design high-performance analog and mixed-signal ... Translate chip-level requirements(data rate, BER, Jitter budget) into detailed block level ...
Chandler, AZ ยท On-site
$198K/yr
Analog Design Engineer Job Responsibility: * Design high-performance analog and mixed-signal ... Translate chip-level requirements(data rate, BER, Jitter budget) into detailed block level ...
Phoenix, AZ ยท On-site
$105K - $200K/yr
Develops the logic design, register transfer level (RTL) coding, and simulation for a CPU required to generate cell libraries, functional units, and the CPU IP block for integration in full chip ...
Phoenix, AZ ยท On-site
$105K - $200K/yr
Develops the logic design, register transfer level (RTL) coding, and simulation for a CPU required to generate cell libraries, functional units, and the CPU IP block for integration in full chip ...
$39.1K - $52.7K
4% of jobs
$52.7K - $66.2K
8% of jobs
$76.1K is the 25th percentile. Wages below this are outliers.
$66.2K - $79.7K
17% of jobs
The median wage is $92.2K / yr.
$79.7K - $93.2K
22% of jobs
$93.2K - $106.7K
15% of jobs
$106.7K - $120.2K
6% of jobs
$124.6K is the 75th percentile. Wages above this are outliers.
$120.2K - $133.7K
7% of jobs
$133.7K - $147.2K
7% of jobs
$147.2K - $160.8K
8% of jobs
$160.8K - $174.3K
2% of jobs
$174.3K - $187.8K
2% of jobs
$39.1K
$106.7K
$187.8K
To excel in Chip Design, a strong background in electrical engineering, digital and analog circuit design, and semiconductor physics is typically required, often supported by a relevant engineering degree. Familiarity with electronic design automation (EDA) tools like Cadence, Synopsys, and Mentor Graphics, as well as proficiency in hardware description languages (HDLs) such as Verilog or VHDL, are standard prerequisites. Outstanding problem-solving skills, attention to detail, and the ability to collaborate closely with cross-functional teams set candidates apart. These competencies are essential for designing efficient, reliable integrated circuits and meeting the evolving needs of the semiconductor industry.
Chip Design offers a clear pathway for career growth, starting from entry-level positions such as Design Engineer or Verification Engineer and progressing to roles like Lead Designer, Project Manager, or Technical Architect. As you gain experience and demonstrate expertise, opportunities often open up in specialized areas such as physical design, timing analysis, or system architecture. Many professionals also advance to leadership or managerial positions, overseeing teams or entire design projects. Additionally, working in such a fast-evolving field keeps you engaged with the latest technologies and can provide options to transition into adjacent areas like product management or application engineering.
A Chip Design job involves creating and developing semiconductor circuits used in electronic devices. Engineers in this field work on designing, verifying, and testing integrated circuits (ICs) to ensure performance, power efficiency, and reliability. They use specialized software tools for designing hardware and optimizing functionality. Chip designers collaborate with cross-functional teams to bring new processors, memory chips, or custom ASICs from concept to production. This role is crucial in industries like computing, telecommunications, and consumer electronics.
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Semiconductor and electronic component manufacturing
11 - 50 Employees
Tempe, AZ, US
2012