Expertise in CMOS semiconductor device physics and test chip design for advanced transistor device architecture. * Experience in scribe line layout design and process monitoring structure development.
Expertise in CMOS semiconductor device physics and test chip design for advanced transistor device architecture. * Experience in scribe line layout design and process monitoring structure development.
Memory array/IP design, memory circuit innovation, test-chip design. * Pre-Si verification, post-Si validation and debugging to enable yield and parametric tracking/ramp. Qualifications: You must ...
Memory array/IP design, memory circuit innovation, test-chip design. * Pre-Si verification, post-Si validation and debugging to enable yield and parametric tracking/ramp. Qualifications: You must ...
Analog IC Design Engineer | LP LVL
Tucson, AZ · On-site
$173K/yr
Lead a full chip design with product ownership and responsibility from definition to release to manufacturing * Direct, guide and participate in activities of a research or technical design function ...
Analog IC Design Engineer | LP LVL
Tucson, AZ · On-site
$173K/yr
Lead a full chip design with product ownership and responsibility from definition to release to manufacturing * Direct, guide and participate in activities of a research or technical design function ...
You will design complex chips that includes various analog and digital control circuitry and work very closely with all aspects of chip design - from writing specifications to developing tests for ...
You will design complex chips that includes various analog and digital control circuitry and work very closely with all aspects of chip design - from writing specifications to developing tests for ...
Principal Digital Engineer (DFT Design)
Chandler, AZ · On-site
$150 - $200/hr
You will design complex chips that includes various analog and digital control circuitry and work very closely with all aspects of chip design - from writing specifications to developing tests for ...
New
Principal Digital Engineer (DFT Design)
Chandler, AZ · On-site
$150 - $200/hr
You will design complex chips that includes various analog and digital control circuitry and work very closely with all aspects of chip design - from writing specifications to developing tests for ...
New
You will design complex chips that includes various analog and digital control circuitry and work very closely with all aspects of chip design - from writing specifications to developing tests for ...
You will design complex chips that includes various analog and digital control circuitry and work very closely with all aspects of chip design - from writing specifications to developing tests for ...
You will design complex chips that includes various analog and digital control circuitry and work very closely with all aspects of chip design - from writing specifications to developing tests for ...
Quick apply
You will design complex chips that includes various analog and digital control circuitry and work very closely with all aspects of chip design - from writing specifications to developing tests for ...
Lead a full chip design with product ownership and responsibility from definition to release to manufacturing * Direct, guide and participate in activities of a research or technical design function ...
Lead a full chip design with product ownership and responsibility from definition to release to manufacturing * Direct, guide and participate in activities of a research or technical design function ...
Hands-on experience inadvanced node test chip design and scribe line optimizationacross 3nm-16nm FinFET or sub-3nm GAA FET technologies, including Backside Power Delivery (BSPD) Preferred ...
Hands-on experience inadvanced node test chip design and scribe line optimizationacross 3nm-16nm FinFET or sub-3nm GAA FET technologies, including Backside Power Delivery (BSPD) Preferred ...
Physical Design Engineer
Phoenix, AZ · On-site
$135K - $139K/yr
Physical Design Develop & own physical design implementation of multi-hierarchy low-power designs ... Exp. in Block-level & Full-chip floor-planning & power grid planning,w/Python, TCL,or Perl progr ...
Physical Design Engineer
Phoenix, AZ · On-site
$135K - $139K/yr
Physical Design Develop & own physical design implementation of multi-hierarchy low-power designs ... Exp. in Block-level & Full-chip floor-planning & power grid planning,w/Python, TCL,or Perl progr ...
SOC Physical Design Static Timing Analysis Engineer
Phoenix, AZ · On-site
$164K - $311K/yr
Work closely with the clocking team and full-chip designers to balance timing fixes, power delivery, clocking, and partitioning. * Collaborate with architecture, clocking design, DFT and logic design ...
SOC Physical Design Static Timing Analysis Engineer
Phoenix, AZ · On-site
$164K - $311K/yr
Work closely with the clocking team and full-chip designers to balance timing fixes, power delivery, clocking, and partitioning. * Collaborate with architecture, clocking design, DFT and logic design ...
SOC Physical Design Static Timing Analysis Engineer
Phoenix, AZ · On-site
$164K - $311K/yr
Work closely with the clocking team and full-chip designers to balance timing fixes, power delivery, clocking, and partitioning. * Collaborate with architecture, clocking design, DFT and logic design ...
SOC Physical Design Static Timing Analysis Engineer
Phoenix, AZ · On-site
$164K - $311K/yr
Work closely with the clocking team and full-chip designers to balance timing fixes, power delivery, clocking, and partitioning. * Collaborate with architecture, clocking design, DFT and logic design ...
Substrate IC Package Design Engineer
Tempe, AZ · On-site
$130 - $160/hr
... design of advanced substrate IC packages and multi-layered interposers. You will play a ... chip-to-chip integration approaches. Working at the intersection of electrical, thermal, and ...
New
Substrate IC Package Design Engineer
Tempe, AZ · On-site
$130 - $160/hr
... design of advanced substrate IC packages and multi-layered interposers. You will play a ... chip-to-chip integration approaches. Working at the intersection of electrical, thermal, and ...
New
Senior Design Verification Engineer
$193K - $290K/yr
Architecting Design Verification environments for ASICs and FPGAs ... Working with RTL, System and software engineers to determine appropriate coverage closure for chip ...
Senior Design Verification Engineer
$193K - $290K/yr
Architecting Design Verification environments for ASICs and FPGAs ... Working with RTL, System and software engineers to determine appropriate coverage closure for chip ...
Copy of Director, Package Design Engineering
Phoenix, AZ · On-site
$135K/yr
Focus on design and development of package and interconnect methods for Renesas's AI/Datacenter ... Knowledge of wafer level, flip-chip, multi-chip module and power devices will be a plus.
Copy of Director, Package Design Engineering
Phoenix, AZ · On-site
$135K/yr
Focus on design and development of package and interconnect methods for Renesas's AI/Datacenter ... Knowledge of wafer level, flip-chip, multi-chip module and power devices will be a plus.
Design Verification Engineer
Chandler, AZ · On-site
$133K - $163K/yr
You will be responsible for end-to-end functional verification across block-level and chip-level ... Design and implement UVM-based testbenches, including infrastructure, scoreboards, checkers, and ...
Design Verification Engineer
Chandler, AZ · On-site
$133K - $163K/yr
You will be responsible for end-to-end functional verification across block-level and chip-level ... Design and implement UVM-based testbenches, including infrastructure, scoreboards, checkers, and ...
Developing detailed block & chip level design documents and collateral. Holding and participating in key design reviews and completion of various checklists. Perform silicon evaluation as required.
Developing detailed block & chip level design documents and collateral. Holding and participating in key design reviews and completion of various checklists. Perform silicon evaluation as required.
* Design and develop package and interconnect methods for Renesas's packaging needs in the areas of Power SiP/modules, WLCSP, multi-chip module with substrate or embedded die/capacitor and power device ...
* Design and develop package and interconnect methods for Renesas's packaging needs in the areas of Power SiP/modules, WLCSP, multi-chip module with substrate or embedded die/capacitor and power device ...
Staff Digital Design Engineer
Chandler, AZ · On-site
$133K/yr
... chip level design documents and collateral. · Holding and participating in key design reviews and completion of various checklists. · Perform silicon evaluation as required. · Document device ...
Quick apply
Staff Digital Design Engineer
Chandler, AZ · On-site
$133K/yr
... chip level design documents and collateral. · Holding and participating in key design reviews and completion of various checklists. · Perform silicon evaluation as required. · Document device ...
Staff Digital Design Engineer
Chandler, AZ · On-site
$133K/yr
... chip level design documents and collateral. • Holding and participating in key design reviews and completion of various checklists. • Perform silicon evaluation as required. • Document device ...
Staff Digital Design Engineer
Chandler, AZ · On-site
$133K/yr
... chip level design documents and collateral. • Holding and participating in key design reviews and completion of various checklists. • Perform silicon evaluation as required. • Document device ...
Chip Design information
See Arizona salary details
$39.1K - $52.7K
4% of jobs
$52.7K - $66.2K
8% of jobs
$76.1K is the 25th percentile. Wages below this are outliers.
$66.2K - $79.7K
17% of jobs
The median wage is $92.2K / yr.
$79.7K - $93.2K
22% of jobs
$93.2K - $106.7K
15% of jobs
$106.7K - $120.2K
6% of jobs
$124.6K is the 75th percentile. Wages above this are outliers.
$120.2K - $133.7K
7% of jobs
$133.7K - $147.2K
7% of jobs
$147.2K - $160.8K
8% of jobs
$160.8K - $174.3K
2% of jobs
$174.3K - $187.8K
2% of jobs
$39.1K
$106.7K
$187.8K
How much do chip design jobs pay per year?
What is a chip design?
A Chip Design job involves creating and developing semiconductor circuits used in electronic devices. Engineers in this field work on designing, verifying, and testing integrated circuits (ICs) to ensure performance, power efficiency, and reliability. They use specialized software tools for designing hardware and optimizing functionality. Chip designers collaborate with cross-functional teams to bring new processors, memory chips, or custom ASICs from concept to production. This role is crucial in industries like computing, telecommunications, and consumer electronics.
What are the key skills and qualifications needed to thrive in chip design?
To excel in Chip Design, a strong background in electrical engineering, digital and analog circuit design, and semiconductor physics is typically required, often supported by a relevant engineering degree. Familiarity with electronic design automation (EDA) tools like Cadence, Synopsys, and Mentor Graphics, as well as proficiency in hardware description languages (HDLs) such as Verilog or VHDL, are standard prerequisites. Outstanding problem-solving skills, attention to detail, and the ability to collaborate closely with cross-functional teams set candidates apart. These competencies are essential for designing efficient, reliable integrated circuits and meeting the evolving needs of the semiconductor industry.
What are the typical career progression opportunities in chip design?
Chip Design offers a clear pathway for career growth, starting from entry-level positions such as Design Engineer or Verification Engineer and progressing to roles like Lead Designer, Project Manager, or Technical Architect. As you gain experience and demonstrate expertise, opportunities often open up in specialized areas such as physical design, timing analysis, or system architecture. Many professionals also advance to leadership or managerial positions, overseeing teams or entire design projects. Additionally, working in such a fast-evolving field keeps you engaged with the latest technologies and can provide options to transition into adjacent areas like product management or application engineering.
How much do chip designers make?
How to get a job in chip design?
Is chip design a good career?
What are the most commonly searched types of Chip Design jobs in Arizona?
The most popular types of Chip Design jobs in Arizona are:
What are popular job titles related to Chip Design jobs in Arizona?
For Chip Design jobs in Arizona, the most frequently searched job titles are:
What job categories do people searching Chip Design jobs in Arizona look for?
The top searched job categories for Chip Design jobs in Arizona are:
What cities in Arizona are hiring for Chip Design jobs?
Cities in Arizona with the most Chip Design job openings:

Full-time
Medical, Retirement, PTO
Re-posted 19 days ago
Intel rating
8.7
Based on 147 frontline employees who took The Breakroom Quiz
19th of 159 rated electronics manufacturers
Job description
Intel is transforming from an Integrated Device Manufacturer (IDM) to a leading foundry service provider, offering world-class manufacturing capabilities to customers worldwide. Our Manufacturing Development and Customer Engineering (MDCE) organization is at the forefront of this transformation, focusing on yield improvement, performance optimization, and exceptional customer service delivery.
We are seeking a Principal Collateral Device Engineer to join our team within MDCE. This role requires regular onsite presence to fulfill essential job responsibilities and will creates next generation device and interconnect technology by ensuring the process device performance for developing processes is world class, using deep understanding of device physics.
Key Responsibilities:
Demonstrated expertise in leading cross functional group in defining derivative architectures including Design rules, transistors and interconnects. Expertise in CMOS semiconductor device physics and test chip design for advanced transistor device architecture.
Experience in scribe line layout design and process monitoring structure development.
Proficiency in design rule development, validation, and waiver management processes.
Strong understanding of DTCO skills Including understanding of SRAM, Standard cells and be the key interface and bridge between Process Integration , Yield, Device and Design.
Strong skills in data analysis, scripting, and statistical techniques for test chip data interpretation.
Excellent technical problem-solving skills with ability to balance design rule compliance with customer flexibility needs.
Ability to work collaboratively in globally diverse, cross-disciplinary teams to develop innovative device collateral solutions.
Demonstrated experience with design of experiment (DOE) principles applied to device collateral optimization.
Proven track record of delivering device collateral solutions in a fast-paced manufacturing environment.
Desire to learn, lead, and influence cross-functional teams in collateral development and design rule optimization.
You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
Minimum Qualifications:
Master's degree in Electrical Engineering, Physics, or related field
15+ years of experience in CMOS device engineering with focus on test chip design and device collateral development
Preferred Qualifications:
Ph.D. degree in Electrical Engineering, Physics, or related field
15+ years of experience in CMOS device engineering and collateral development
Hands-on experience in advanced node test chip design and scribe line optimization for 3nm-16nm FinFETs and sub 3nm GAA FETs
Experience with design rule checker (DRC) development and physical verification flows
Experience in High-Volume Manufacturing environment with focus on yield monitoring and process control structures
Knowledge of statistical process control (SPC) and advanced data analytics for device collateral optimization
Knowledge of mask generation including Boolean/OPC .
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.
Annual Salary Range for jobs which could be performed in the US: $224,970.00-317,600.00 USDThe range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.*
ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.About Intel
Sourced by ZipRecruiter
Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore's Law to bring smart, connected devices to every person on Earth
Industry
Manufacturing
Company size
10,000+ Employees
Headquarters location
Santa Clara, CA, US
Year founded
1968