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Chip Design Jobs (NOW HIRING)

Eridu AI

ASIC Chip Design Lead

Saratoga, CA · On-site

$250K - $280K/yr

Position Overview We are seeking a hands-on ASIC Chip Design Lead to own chip design execution from micro-architecture through full-chip integration and timing signoff. This role sits between senior ...

Pied Piper

Semiconductor Chip Expert

Austin, TX

Design and develop semiconductor chips * Conduct research to improve chip performance and functionality * Collaborate with cross-functional teams to ensure successful chip design and production

Oxford Ionics

Senior QPU Design Engineer

College Park, MD · On-site

$126K - $181K/yr

Guiding the end to end chip design process, from requirements to layout and tape-out. * Coordinating with other teams to ensure feasibility and compatibility between the various layers of the chip.

Apple

CAD Engineer - PDV

Austin, TX · On-site

As part of our Silicon Technologies group, you'll help design and manufacture our next-generation, high-performance, power-efficient processor, system-on-chip (SoC). You'll ensure Apple products and ...

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Chip Design information

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$42K

$114.5K

$201.5K

How much do chip design jobs pay per year?

As of Jul 17, 2026, the average yearly pay for chip design in the United States is $114,491.00, according to ZipRecruiter salary data. Most workers in this role earn between $83,500.00 and $144,000.00 per year, depending on experience, location, and employer.

What are the key skills and qualifications needed to thrive in the Chip Design position, and why are they important?

To excel in Chip Design, a strong background in electrical engineering, digital and analog circuit design, and semiconductor physics is typically required, often supported by a relevant engineering degree. Familiarity with electronic design automation (EDA) tools like Cadence, Synopsys, and Mentor Graphics, as well as proficiency in hardware description languages (HDLs) such as Verilog or VHDL, are standard prerequisites. Outstanding problem-solving skills, attention to detail, and the ability to collaborate closely with cross-functional teams set candidates apart. These competencies are essential for designing efficient, reliable integrated circuits and meeting the evolving needs of the semiconductor industry.

What are the typical career progression opportunities in a Chip Design role?

Chip Design offers a clear pathway for career growth, starting from entry-level positions such as Design Engineer or Verification Engineer and progressing to roles like Lead Designer, Project Manager, or Technical Architect. As you gain experience and demonstrate expertise, opportunities often open up in specialized areas such as physical design, timing analysis, or system architecture. Many professionals also advance to leadership or managerial positions, overseeing teams or entire design projects. Additionally, working in such a fast-evolving field keeps you engaged with the latest technologies and can provide options to transition into adjacent areas like product management or application engineering.

Is chip design a good career?

Chip design is a specialized field within electronics engineering focused on creating integrated circuits and microchips. It offers high demand, competitive salaries, and opportunities to work with advanced technology, but requires strong skills in electronics, programming, and often a relevant degree or certification. Career growth depends on industry trends and individual expertise in areas like VLSI design and CAD tools.

How do you become a chip designer?

To become a chip designer, typically a candidate needs a bachelor's degree in electrical engineering, computer engineering, or a related field, along with strong skills in digital logic, circuit design, and hardware description languages like VHDL or Verilog. Gaining experience through internships, developing proficiency with CAD tools, and staying updated on industry standards are also important steps in pursuing a career in chip design.

What is a Chip Design job?

A Chip Design job involves creating and developing semiconductor circuits used in electronic devices. Engineers in this field work on designing, verifying, and testing integrated circuits (ICs) to ensure performance, power efficiency, and reliability. They use specialized software tools for designing hardware and optimizing functionality. Chip designers collaborate with cross-functional teams to bring new processors, memory chips, or custom ASICs from concept to production. This role is crucial in industries like computing, telecommunications, and consumer electronics.

How much do chip designers make?

Chip designers, also known as integrated circuit designers, typically earn between $80,000 and $150,000 annually, depending on experience, education, and location. Senior roles or those with specialized skills in hardware description languages and CAD tools can earn higher salaries, often exceeding $200,000.

What engineer makes $500,000 a year?

Senior chip design engineers with extensive experience, advanced skills in hardware description languages, and expertise in complex integrated circuit development can earn salaries approaching or exceeding $500,000 annually, especially in high-cost living areas or within leading technology companies. Such roles often require advanced degrees, certifications, and a strong track record of successful project delivery.
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What cities are hiring for Chip Design jobs? Cities with the most Chip Design job openings:
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Chip Design jobs near you
Infographic showing various Chip Design job openings in the United States as of July 2026, with employment types broken down into 17% Internship, 49% Full Time, 17% Part Time, and 17% Nights. Highlights an 100% In-person job distribution, with an average salary of $114,491 per year, or $55 per hour.

ASIC Chip Design Lead

Eridu AI

Saratoga, CA • On-site

$250K - $280K/yr

Full-time

Re-posted 15 days ago

Job description

About Eridu
Eridu is a Silicon Valley-based hardware startup pioneering infrastructure solutions that accelerate AI data centers to deliver Faster AI. Today's AI performance is frequently limited by communication bottlenecks. Eridu introduces multiple industry-first innovations across silicon, packaging, software, and systems to deliver an order of magnitude improvement in performance and unlock greater GPU utilization to speed training job completion times and tokens-per-second for more profitable inference. We do this while simultaneously reducing capital and power costs and improving reliability.
The company's solutions and value proposition have been widely validated by leading hyperscalers.
Eridu has raised over $200M to date including its most recent, oversubscribed Series A round. The company is led by a veteran team of Silicon Valley executives who have delivered multiple billion dollar product lines and led multiple companies to billion dollar exits, including serial entrepreneur Drew Perkins, co-founder of Infinera (NASDAQ: INFN), Lightera (acq. by Ciena), Gainspeed (acq. by Nokia) and Mojo Vision (the world's leading micro-LED company). The company is in execution mode and has a world-class engineering team with decades of experience in state-of-the-art silicon, packaging, optics, software, and systems. Eridu is working with best-in-class supply chain partners including silicon, packaging and systems.
Visit our website eridu.ai to learn more.
Position Overview
We are seeking a hands-on ASIC Chip Design Lead to own chip design execution from micro-architecture through full-chip integration and timing signoff. This role sits between senior individual contributor and technical lead: you will personally drive RTL and micro-architecture while providing execution leadership across design, verification, and physical design teams.
This is a highly technical, roll-up-your-sleeves role for someone who has taken chips to tape-out, understands what breaks late in the cycle, and knows how to drive designs to closure in a fast-paced startup environment.
Responsibilities
Hands-on RTL Development
  • Write, review, and debug production-quality RTL in Verilog/SystemVerilog
  • Own RTL blocks end-to-end from specification through signoff
  • Make timing-, area-, and power-aware design decisions at the RTL and micro-architecture levels
  • Perform detailed code reviews and set a high technical bar for RTL quality
Micro-Architecture Specification
  • Draft detailed micro-architecture specifications derived from architecture documents and feature requirements
  • Translate high-level requirements into implementable pipelines, control logic, datapaths, interfaces, and corner-case handling
  • Clearly define performance, latency, and resource tradeoffs to unblock RTL and verification execution
Physical-Design-Aware Design & Timing Closure
  • Work closely with Physical Design to improve synthesis and place-and-route timing.
  • Iterate on RTL, hierarchy, micro-architecture, and floorplanning to address timing, congestion, and QoR issues
  • Analyze synthesis and P&R reports and proactively drive timing, area, and power improvements
Verification Collaboration & Debug
  • Partner with Design Verification to debug functional and performance issues
  • Review functional and code coverage and provide actionable feedback
  • Own bugs from discovery through fix, validation, and closure
Full-Chip Integration & Signoff
  • Own full-chip RTL integration and block roll-up
  • Run chip-level synthesis, define constraints, and close chip-level timing
  • Deliver timing-clean netlists to Physical Design that meet performance targets
Execution Discipline & Technical Leadership
  • Drive block- and chip-level design checklists as execution quality gates
  • Review checklist status with designers and proactively push closure of open items
  • Continuously refine design methodologies, checklists, and flows based on silicon learnings
  • Lead by technical authority and hands-on execution rather than coordination alone

Qualifications
  • Strong hands-on experience with RTL design and micro-architecture
  • Proven experience with full-chip integration and timing closure
  • Led at least one full-chip tape-out within the last 3 years, with direct responsibility for design signoff and PD handoff
  • Deep understanding of synthesis, static timing analysis, and physical-design collaboration
  • Experience refactoring and restructuring RTL to resolve timing, area, and congestion challenges
  • Comfortable working cross-functionally with architecture, verification, firmware, and physical design teams
  • Demonstrated ability to drive execution in ambiguous, fast-moving environments

Nice to Have
  • Silicon bring-up experience, including post-silicon debug and RTL-to-silicon correlation
  • Hands-on experience defining and refining SDC constraints and improving post-layout timing
  • Knowledge of high-performance networking architectures and Ethernet-based systems
  • Familiarity with Ultra Ethernet and/or UCIe chip-to-chip interconnect protocols
  • Experience with chiplet-based system design

Why Join Us?
At Eridu, you'll have the opportunity to shape the future of AI infrastructure, working with a world-class team on groundbreaking technology that pushes the boundaries of AI performance. Your contributions will directly impact the next generation of AI infrastructure solutions, transforming the performance of AI data centers.
The starting base salary for the selected candidate will be established based on their relevant skills, experience, qualifications, work location, market trends, and the compensation of employees in comparable roles.
Notice to Recruiting Agencies
Eridu does not accept unsolicited resumes or candidate profiles from staffing agencies or third-party recruiters. Any candidate submitted to Eridu without prior written authorization from our recruiting team will be considered unsolicited and will become the property of Eridu. Eridu reserves the right to pursue and hire such candidates without any obligation to pay fees. Recruiting agencies are expressly instructed not to contact hiring managers, employees, or executives regarding open positions.
The pay range for this role is:
250,000 - 280,000 USD per year (Saratoga, CA)

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