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Director Chip Design Jobs (NOW HIRING)

Eridu AI

ASIC Chip Design Lead

Saratoga, CA · On-site

$250K - $280K/yr

Led at least one full-chip tape-out within the last 3 years, with direct responsibility for design signoff and PD handoff * Deep understanding of synthesis, static timing analysis, and physical ...

Rambus

PE CAD Engineering

San Jose, CA

$126K - $234K/yr

Overview Rambus, a premier chip and silicon IP provider, is seeking to hire an exceptional CAD ... As a CAD Infrastructure Engineer, the candidate will be reporting to the Director of CAD. In this ...

Rambus

PE CAD Engineering

San Jose, CA

$126K - $234K/yr

Rambus, a premier chip and silicon IP provider, is seeking to hire an exceptional CAD ... As a CAD Infrastructure Engineer, the candidate will be reporting to the Director of CAD. In this ...

Rambus

PE CAD Engineering

San Jose, CA · On-site

$126K - $234K/yr

Overview Rambus, a premier chip and silicon IP provider, is seeking to hire an exceptional CAD ... As a CAD Infrastructure Engineer, the candidate will be reporting to the Director of CAD. In this ...

Apple

GPU Physical Design Clocking Engineer

Austin, TX · On-site

$134K - $138K/yr

You will be implementing complete chip design from netlist to tapeout. You will have hands on ... directly and or directing a team of engineers to innovate and execute on world class designs.

Apple

GPU Physical Design Engineer

Austin, TX · On-site

$134K - $138K/yr

In this role, you will: - Work closely with the FE team to understand chip architecture and drive ... directing a team of engineers to innovate and execute on world class GPU designs.

Apple

GPU Physical Design Engineer

Austin, TX · On-site

$134K - $138K/yr

In this role, you will: - Work closely with the FE team to understand chip architecture and drive ... directing a team of engineers to innovate and execute on world class GPU designs.

AvicenaTech

ASIC Design Verification Engineer

Sunnyvale, CA · On-site

$159K - $194K/yr

... to-chip communications. This technology will revolutionize High-Performance (HPC) and Cloud ... Develop constrained-random, directed, and stress tests, as well as necessary sequences, scores, and ...

Apple

GPU Top Level Physical Design Engineer

Austin, TX · On-site

$134K - $138K/yr

You will be responsible for implementing complete chip design from netlist to tapeout. You will ... directly and or directing a team of engineers to innovate and execute on world class designs.

Apple

GPU Top Level Physical Design Engineer

Austin, TX · On-site

$134K - $138K/yr

You will be responsible for implementing complete chip design from netlist to tapeout. You will ... directly and or directing a team of engineers to innovate and complete world class designs.

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How much do director chip design jobs pay per year?

As of Jun 5, 2026, the average yearly pay for director chip design in the United States is $135,763.00, according to ZipRecruiter salary data. Most workers in this role earn between $109,500.00 and $163,000.00 per year, depending on experience, location, and employer.

What are the key skills and qualifications needed to thrive as a Director of Chip Design, and why are they important?

To thrive as a Director of Chip Design, you need deep expertise in semiconductor design, electrical engineering, and project management, typically backed by an advanced degree and significant industry experience. Familiarity with EDA tools like Cadence or Synopsys, knowledge of ASIC/FPGA design flows, and relevant certifications are often required. Exceptional leadership, strategic thinking, and communication skills help drive innovation and coordinate cross-functional teams. These competencies ensure the successful delivery of complex chip projects that meet technical, budget, and time objectives in a highly competitive industry.

What are some common challenges a Director of Chip Design faces when leading multidisciplinary engineering teams?

A Director of Chip Design often manages teams that include digital, analog, verification, and layout engineers, making cross-functional communication and alignment essential. One common challenge is balancing project timelines with the need for innovation and rigorous testing to ensure chip reliability and performance. Additionally, staying ahead of rapidly evolving semiconductor technologies and managing resources across multiple concurrent projects can be demanding. Effective directors foster a collaborative environment, resolve technical conflicts, and ensure that all teams work towards shared goals.

What does a Director of Chip Design do?

A Director of Chip Design oversees the entire process of designing integrated circuits (ICs) or microchips, managing teams of engineers and ensuring that projects meet technical and business requirements. This role involves setting the vision and strategy for chip development, collaborating with cross-functional teams, and ensuring timely delivery of high-quality products. The director is responsible for resource allocation, project management, and fostering innovation to keep up with industry trends. Additionally, they ensure compliance with industry standards and drive continuous improvement in design methodologies.
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What cities are hiring for Director Chip Design jobs? Cities with the most Director Chip Design job openings:
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Director Chip Design jobs near you
Infographic showing various Director Chip Design job openings in the United States as of May 2026, with employment types broken down into 8% Internship, 64% Full Time, 8% Part Time, 16% Temporary, and 4% Contract. Highlights an 95% Physical, 2% Hybrid, and 3% Remote job distribution, with an average salary of $135,763 per year, or $65.3 per hour.

ASIC Chip Design Lead

Eridu AI

Saratoga, CA • On-site

$250K - $280K/yr

Full-time

Posted 2 days ago

Job description

About Eridu
Eridu is a Silicon Valley-based hardware startup pioneering infrastructure solutions that accelerate AI data centers to deliver Faster AI. Today's AI performance is frequently limited by communication bottlenecks. Eridu introduces multiple industry-first innovations across silicon, packaging, software, and systems to deliver an order of magnitude improvement in performance and unlock greater GPU utilization to speed training job completion times and tokens-per-second for more profitable inference. We do this while simultaneously reducing capital and power costs and improving reliability.
The company's solutions and value proposition have been widely validated by leading hyperscalers.
Eridu has raised over $200M to date including its most recent, oversubscribed Series A round. The company is led by a veteran team of Silicon Valley executives who have delivered multiple billion dollar product lines and led multiple companies to billion dollar exits, including serial entrepreneur Drew Perkins, co-founder of Infinera (NASDAQ: INFN), Lightera (acq. by Ciena), Gainspeed (acq. by Nokia) and Mojo Vision (the world's leading micro-LED company). The company is in execution mode and has a world-class engineering team with decades of experience in state-of-the-art silicon, packaging, optics, software, and systems. Eridu is working with best-in-class supply chain partners including silicon, packaging and systems.
Visit our website eridu.ai to learn more.
Position Overview
We are seeking a hands-on ASIC Chip Design Lead to own chip design execution from micro-architecture through full-chip integration and timing signoff. This role sits between senior individual contributor and technical lead: you will personally drive RTL and micro-architecture while providing execution leadership across design, verification, and physical design teams.
This is a highly technical, roll-up-your-sleeves role for someone who has taken chips to tape-out, understands what breaks late in the cycle, and knows how to drive designs to closure in a fast-paced startup environment.
Responsibilities
Hands-on RTL Development
  • Write, review, and debug production-quality RTL in Verilog/SystemVerilog
  • Own RTL blocks end-to-end from specification through signoff
  • Make timing-, area-, and power-aware design decisions at the RTL and micro-architecture levels
  • Perform detailed code reviews and set a high technical bar for RTL quality
Micro-Architecture Specification
  • Draft detailed micro-architecture specifications derived from architecture documents and feature requirements
  • Translate high-level requirements into implementable pipelines, control logic, datapaths, interfaces, and corner-case handling
  • Clearly define performance, latency, and resource tradeoffs to unblock RTL and verification execution
Physical-Design-Aware Design & Timing Closure
  • Work closely with Physical Design to improve synthesis and place-and-route timing.
  • Iterate on RTL, hierarchy, micro-architecture, and floorplanning to address timing, congestion, and QoR issues
  • Analyze synthesis and P&R reports and proactively drive timing, area, and power improvements
Verification Collaboration & Debug
  • Partner with Design Verification to debug functional and performance issues
  • Review functional and code coverage and provide actionable feedback
  • Own bugs from discovery through fix, validation, and closure
Full-Chip Integration & Signoff
  • Own full-chip RTL integration and block roll-up
  • Run chip-level synthesis, define constraints, and close chip-level timing
  • Deliver timing-clean netlists to Physical Design that meet performance targets
Execution Discipline & Technical Leadership
  • Drive block- and chip-level design checklists as execution quality gates
  • Review checklist status with designers and proactively push closure of open items
  • Continuously refine design methodologies, checklists, and flows based on silicon learnings
  • Lead by technical authority and hands-on execution rather than coordination alone

Qualifications
  • Strong hands-on experience with RTL design and micro-architecture
  • Proven experience with full-chip integration and timing closure
  • Led at least one full-chip tape-out within the last 3 years, with direct responsibility for design signoff and PD handoff
  • Deep understanding of synthesis, static timing analysis, and physical-design collaboration
  • Experience refactoring and restructuring RTL to resolve timing, area, and congestion challenges
  • Comfortable working cross-functionally with architecture, verification, firmware, and physical design teams
  • Demonstrated ability to drive execution in ambiguous, fast-moving environments

Nice to Have
  • Silicon bring-up experience, including post-silicon debug and RTL-to-silicon correlation
  • Hands-on experience defining and refining SDC constraints and improving post-layout timing
  • Knowledge of high-performance networking architectures and Ethernet-based systems
  • Familiarity with Ultra Ethernet and/or UCIe chip-to-chip interconnect protocols
  • Experience with chiplet-based system design

Why Join Us?
At Eridu, you'll have the opportunity to shape the future of AI infrastructure, working with a world-class team on groundbreaking technology that pushes the boundaries of AI performance. Your contributions will directly impact the next generation of AI infrastructure solutions, transforming the performance of AI data centers.
The starting base salary for the selected candidate will be established based on their relevant skills, experience, qualifications, work location, market trends, and the compensation of employees in comparable roles.
Notice to Recruiting Agencies
Eridu does not accept unsolicited resumes or candidate profiles from staffing agencies or third-party recruiters. Any candidate submitted to Eridu without prior written authorization from our recruiting team will be considered unsolicited and will become the property of Eridu. Eridu reserves the right to pursue and hire such candidates without any obligation to pay fees. Recruiting agencies are expressly instructed not to contact hiring managers, employees, or executives regarding open positions.
The pay range for this role is:
250,000 - 280,000 USD per year (Saratoga, CA)

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