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Director Chip Design Jobs in Seattle, WA (NOW HIRING)

K2 Space

Senior ASIC Design Verification Engineer

Seattle, WA · On-site

$170K - $250K/yr

  • Medical

  • Dental

  • Vision

  • Life

  • PTO

Develop and execute verification plans for block-level, subsystem-level, and full-chip environments ... Drive constrained-random and directed testing strategies to validate functionality, corner cases ...

K2 Space

Senior ASIC Design Verification Engineer

Seattle, WA · On-site

$170K - $250K/yr

  • Medical

  • Dental

  • Vision

  • Life

  • PTO

Develop and execute verification plans for block-level, subsystem-level, and full-chip environments ... Drive constrained-random and directed testing strategies to validate functionality, corner cases ...

K2 Space

Principal ASIC Design Verification Engineer

Seattle, WA · On-site

$190K - $285K/yr

  • Medical

  • Dental

  • Vision

  • Life

  • PTO

Develop and execute verification plans for block-level, subsystem-level, and full-chip environments ... Drive constrained-random and directed testing strategies to validate functionality, corner cases ...

Blue Origin

Principal RFIC Design Engineer - TeraWave

Seattle, WA · On-site

$213K - $298K/yr

  • Medical

  • Dental

  • Vision

  • Life

  • Retirement

  • PTO

Design and develop RFICs, and mixed-signal ASICs * Implement designs using Cadence Virtuoso ... Direct Tape out Experience in taping out an RF or deep sub-micron Analog mix signal chip Preferred ...

Targeted Talent

Compiler Tech Lead

Seattle, WA · On-site

$170K - $190K/yr

  • Medical

  • PTO

Responsibilities: * Design and implement software that maps neural nets onto our spatial ... Driven and self-directed * Proficiency in a variety of development styles and languages * Strong ...

RogueBeam

RF/Microwave Engineer

Seattle, WA · On-site

$120 - $180/hr

... direct line of sight from algorithm to deployed system.We're early, we're growing fast, and the ... Design RF/microwave circuits, MMICs, passive/printed components, substrates, chip break-outs ...

Roguebeam

EE Hardware Engineer

Seattle, WA · On-site

$90 - $130/hr

... direct line of sight from algorithm to deployed system.We're early, we're growing fast, and the ... Your work will include system design (e.g. driving requirements for silicon chip development and ...

Crusoe

Staff Technical Program Manager, Deployments

Seattle, WA · On-site

$146K - $190K/yr

  • Medical

  • Dental

  • Vision

  • Life

  • Retirement

  • PTO

We build and operate GPU infrastructure powered by clean energy, from data center design through ... Our TPMs define and drive the entire deployment engagement model from chip vendor engagement ...

Divensi

Full Stack Developer

Redmond, WA

We've helped countless blue chip and mid-size companies drive innovation, increase productivity ... Design, coding, debugging, time management, communication skills are essential. Experience Required ...

Divensi

Full Stack Developer

Redmond, WA · On-site

We've helped countless blue chip and mid-size companies drive innovation, increase productivity ... Design, coding, debugging, time management, communication skills are essential. Experience Required ...

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All JobsChip Design JobsDirector Chip Design JobsDirector Chip Design Jobs in Seattle, WA

Director Chip Design information

See Seattle, WA salary details

$42.1K

$154.5K

$276.5K

How much do director chip design jobs pay per year?

As of Aug 18, 2026, the average yearly pay for director chip design in Seattle, WA is $154,502.00, according to ZipRecruiter salary data. Most workers in this role earn between $124,600.00 and $185,500.00 per year, depending on experience, location, and employer.

What does a director of chip design do?

A Director of Chip Design oversees the entire process of designing integrated circuits (ICs) or microchips, managing teams of engineers and ensuring that projects meet technical and business requirements. This role involves setting the vision and strategy for chip development, collaborating with cross-functional teams, and ensuring timely delivery of high-quality products. The director is responsible for resource allocation, project management, and fostering innovation to keep up with industry trends. Additionally, they ensure compliance with industry standards and drive continuous improvement in design methodologies.

What are the key skills and qualifications needed to thrive as a director of chip design?

To thrive as a Director of Chip Design, you need deep expertise in semiconductor design, electrical engineering, and project management, typically backed by an advanced degree and significant industry experience. Familiarity with EDA tools like Cadence or Synopsys, knowledge of ASIC/FPGA design flows, and relevant certifications are often required. Exceptional leadership, strategic thinking, and communication skills help drive innovation and coordinate cross-functional teams. These competencies ensure the successful delivery of complex chip projects that meet technical, budget, and time objectives in a highly competitive industry.

What are some common challenges a director of chip design faces when leading multidisciplinary engineering teams?

A Director of Chip Design often manages teams that include digital, analog, verification, and layout engineers, making cross-functional communication and alignment essential. One common challenge is balancing project timelines with the need for innovation and rigorous testing to ensure chip reliability and performance. Additionally, staying ahead of rapidly evolving semiconductor technologies and managing resources across multiple concurrent projects can be demanding. Effective directors foster a collaborative environment, resolve technical conflicts, and ensure that all teams work towards shared goals.

What are the most commonly searched types of Chip Design jobs in Seattle, WA?

The most popular types of Chip Design jobs in Seattle, WA are:

What are popular job titles related to Director Chip Design jobs in Seattle, WA?

For Director Chip Design jobs in Seattle, WA, the most frequently searched job titles are:

What job categories do people searching Director Chip Design jobs in Seattle, WA look for?

The top searched job categories for Director Chip Design jobs in Seattle, WA are:

Director Chip Design jobs near you

Senior ASIC Design Verification Engineer

K2 Space

Seattle, WA • On-site

$170K - $250K/yr

Full-time

Medical, Dental, Vision, Life, PTO

Re-posted 18 days ago

Job description

The Role 

We are seeking a Senior ASIC Design Verification Engineer whose role will be to verify the functionality, performance, and robustness of our custom silicon designs. You will help define the verification approach, contribute to methodology, and work closely with architecture, RTL design, DFT, firmware, physical design, and silicon validation engineers. This is a hands-on role with high ownership, deep technical engagement, and the opportunity to shape first-generation silicon. 

Responsibilities 

  • Develop and execute verification plans for block-level, subsystem-level, and full-chip environments. Build SystemVerilog/UVM test benches, including agents, monitors, scoreboards, checkers, and coverage models.
  • Write SystemVerilog Assertions (SVA) and integrate formal verification where appropriate.
  • Drive constrained-random and directed testing strategies to validate functionality, corner cases, and stress scenarios.
  • Run simulations, triage failures, drive root-cause analysis, and collaborate with RTL designers to resolve issues.
  • Implement and maintain functional coverage, code coverage, assertion coverage, and ensure coverage closure for sign-off.
  • Manage regression testing, simulation farms, and CI pipelines to ensure high test throughput and fast debug iterations.
  • Participate in design reviews, microarchitecture discussions, and influence design-for-verification (DFV) best practices.
  • Work closely with architecture, RTL design, DFT, firmware, physical design, and silicon validation engineers to ensure end-to-end coverage and test.
  • Support silicon bring-up and post-silicon validation through test reuse, diagnostics, and debug analysis.
  • Participate in ASIC team interviews.
  • Contribute to advancement of DV methodologies and improvements.
  • Engage external IP providers and verification partners when needed. 

Qualifications 

  • B.S. or M.S. in Electrical Engineering, Computer Engineering, or related field.
  • 5+ years of experience in ASIC/SoC verification.
  • Solid understanding of SystemVerilog, digital logic, RTL design, and hardware verification flows.
  • Proficiency with a simulation (VCS, Xcelium, Questa), waveform debug (Verdi, SimVision), coverage tool, and scripting languages (ex: Python, Perl, TCL).
  • Experience with testplanning, UVM-based testbench development, constrained-random testing, functional coverage, and SystemVerilog assertions.
  • Experience with regression management, coverage analysis, revision control (Git), and CI/CD automation.
  • Understanding of several industry-standard interfaces (ex: APB/AHB/AXI).
  • Familiarity with embedded processor-based designs and firmware/bare metal coding (ex: C, C++). 

Nice to Have

  • Experience with developing and integrating reference models.
  • Understanding of low power verification.
  • Familiarity with gate-level simulation and analog behavioral models.
  • Involvement in post-silicon validation planning and execution.
  • Experience working in cross-functional, geographically distributed teams.
  • Experience in space, telecom, or RF/digital mixed systems is a plus. 

Compensation and Benefits:

  • Base salary range for this role is $170,000 - $250,000 + equity in the company
  • Salary will be based on several factors including, but not limited to: knowledge and skills, education, and experience level
  • Comprehensive benefits package including paid time off, medical/dental/vision/ coverage, life insurance, paid parental leave, and many other perks
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About K2 Space

Sourced by ZipRecruiter

Industry

Guided missile and space vehicle manufacturing

Company size

11 - 50 Employees

Headquarters location

Los Angeles, CA, US

Year founded

2022

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