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Director Chip Design Jobs (NOW HIRING)

GPU Top Level Physical Design Engineer

Austin, TX ยท On-site

$134K - $138K/yr

You will be responsible for implementing complete chip design from netlist to tapeout. You will ... directly and or directing a team of engineers to innovate and execute on world class designs.

GPU Top Level Physical Design Engineer

Austin, TX ยท On-site

$134K - $138K/yr

You will be responsible for implementing complete chip design from netlist to tapeout. You will ... directly and or directing a team of engineers to innovate and complete world class designs.

GPU Physical Design Clocking Engineer

Austin, TX ยท On-site

$134K - $138K/yr

You will be implementing complete chip design from netlist to tapeout. You will have hands on ... and or directing a team of engineers to innovate and execute on world class designs.

GPU Physical Design Engineer

Austin, TX ยท On-site

$134K - $138K/yr

Work closely with the FE team to understand chip architecture and drive physical aspects early in ... or directing a team of engineers to innovate and execute on world class GPU designs. Apple is an ...

Description In this role, you will: - Work closely with the FE team to understand chip architecture ... directing a team of engineers to innovate and execute on world class GPU designs. Minimum ...

Description In this role, you will: - Work closely with the FE team to understand chip architecture ... directing a team of engineers to innovate and execute on world class GPU designs. Minimum ...

GPU Physical Design Engineer

Austin, TX ยท On-site

$181K - $318K/yr

Description In this role, you will: - Work closely with the FE team to understand chip architecture ... directing a team of engineers to innovate and execute on world class GPU designs. Minimum ...

Description In this role, you will: - Work closely with the FE team to understand chip architecture ... directing a team of engineers to innovate and execute on world class GPU designs. Minimum ...

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Director Chip Design information

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$37K

$135.8K

$243K

How much do director chip design jobs pay per year?

As of Jun 5, 2026, the average yearly pay for director chip design in the United States is $135,763.00, according to ZipRecruiter salary data. Most workers in this role earn between $109,500.00 and $163,000.00 per year, depending on experience, location, and employer.

What are the key skills and qualifications needed to thrive as a Director of Chip Design, and why are they important?

To thrive as a Director of Chip Design, you need deep expertise in semiconductor design, electrical engineering, and project management, typically backed by an advanced degree and significant industry experience. Familiarity with EDA tools like Cadence or Synopsys, knowledge of ASIC/FPGA design flows, and relevant certifications are often required. Exceptional leadership, strategic thinking, and communication skills help drive innovation and coordinate cross-functional teams. These competencies ensure the successful delivery of complex chip projects that meet technical, budget, and time objectives in a highly competitive industry.

What are some common challenges a Director of Chip Design faces when leading multidisciplinary engineering teams?

A Director of Chip Design often manages teams that include digital, analog, verification, and layout engineers, making cross-functional communication and alignment essential. One common challenge is balancing project timelines with the need for innovation and rigorous testing to ensure chip reliability and performance. Additionally, staying ahead of rapidly evolving semiconductor technologies and managing resources across multiple concurrent projects can be demanding. Effective directors foster a collaborative environment, resolve technical conflicts, and ensure that all teams work towards shared goals.

What does a Director of Chip Design do?

A Director of Chip Design oversees the entire process of designing integrated circuits (ICs) or microchips, managing teams of engineers and ensuring that projects meet technical and business requirements. This role involves setting the vision and strategy for chip development, collaborating with cross-functional teams, and ensuring timely delivery of high-quality products. The director is responsible for resource allocation, project management, and fostering innovation to keep up with industry trends. Additionally, they ensure compliance with industry standards and drive continuous improvement in design methodologies.
More about Director Chip Design jobs
What cities are hiring for Director Chip Design jobs? Cities with the most Director Chip Design job openings:
What are the most commonly searched types of Chip Design jobs? The most popular types of Chip Design jobs are:
What states have the most Director Chip Design jobs? States with the most job openings for Director Chip Design jobs include:
What job categories do people searching Director Chip Design jobs look for? The top searched job categories for Director Chip Design jobs are:
Infographic showing various Director Chip Design job openings in the United States as of May 2026, with employment types broken down into 8% Internship, 64% Full Time, 8% Part Time, 16% Temporary, and 4% Contract. Highlights an 95% Physical, 2% Hybrid, and 3% Remote job distribution, with an average salary of $135,763 per year, or $65.3 per hour.
Physical Design Engineer, Forward Deployed Engineering

Physical Design Engineer, Forward Deployed Engineering

OpenAI

San Francisco, CA โ€ข On-site

$162K - $302K/yr

Full-time

Posted 22 days ago


Job description

About the Team
OpenAI's Forward Deployed Engineering team partners with leading semiconductor companies to deploy production-grade AI systems across the entire chip design lifecycle: design, verification, and physical design. We operate at the intersection of customer delivery and core platform development, embedding deeply with customers to translate frontier model capabilities into systems that materially improve engineering workflows and accelerate innovation.
Our work turns early, high-touch deployments into repeatable solution patterns, reference architectures, and evaluation practices that scale across the semiconductor ecosystem.
About the Role
We are seeking a highly skilled Physical Design Engineer to join our semiconductor-focused Forward Deployed Engineering team. This is a senior IC role that will begin with a strong emphasis on physical design expertise, technical judgment, advisory leverage, and customer credibility, with the expectation that the person will grow into a broader Forward Deployed Engineering role over time.
In the near term, you will serve as the team's physical design SME across semiconductor deployments: helping FDEs, Product, and Research understand backend implementation workflows, pressure-test AI-assisted solution ideas against real physical design constraints, and raise the quality of our customer-facing technical work. You will help the broader team build fluency in implementation flows, EDA tooling, signoff methodology, and the trade-offs that shape physical design decisions in practice.
Over time, we expect this role to expand beyond SME support into broader FDE ownership: partnering directly with customers, shaping deployment strategy, building and iterating production-grade AI systems, driving technical workstreams, and helping turn high-touch semiconductor deployments into repeatable solutions.
This is a strong fit for someone who brings deep physical design expertise today and is excited to grow into a customer-facing, systems-building, delivery-oriented FDE role.
In this role, you will:
  • Serve as the physical design SME for semiconductor customer engagements, helping FDE teams understand backend implementation workflows, constraints, and opportunities
  • Partner with FDEs during customer discovery and scoping to translate ambiguous pain points into clear solution hypotheses, success criteria, and technical plans
  • Support customer-facing technical conversations as a trusted advisor, engaging credibly with technical leaders
  • Help shape AI-assisted solutions across physical design workflows, including floorplanning, place and route, clocking, timing closure, congestion, power, physical verification, and signoff
  • Guide feasibility and integration decisions across the entire chip design lifecycle: design, verification, and physical design
  • Partner with FDEs and customer SMEs to curate evaluation datasets, golden tasks, rubrics, and acceptance criteria for physical design use cases, ensuring evals reflect real workflows and meaningful success metrics
  • Build or guide lightweight prototypes, benchmarks, methodology experiments, and internal tools that validate opportunities and accelerate solution development
  • Educate and mentor the broader FDE team on physical design concepts, implementation flows, EDA tooling, and key trade-offs so the org can engage customers with greater depth and confidence
  • Surface repeated customer signal to Product and Research to help shape roadmap, model behavior, and platform capabilities for semiconductor use cases
  • Progressively take on broader FDE responsibilities, including customer discovery, solution architecture, prototype development, production deployment, and ownership of technical workstreams

Minimim Qualifications
  • BS with 7+ years, MS with 5+ years, or equivalent industry experience in physical design, physical implementation, or backend signoff for complex ASIC or SoC programs
  • Demonstrated success bringing complex designs through tapeout, with hands-on experience in floorplanning, place and route, CTS, timing closure, power analysis, physical verification, and signoff
  • Deep familiarity with industry-standard EDA tools and flows for synthesis, PNR, STA, physical verification, equivalence checking, and power analysis
  • Strong understanding of how physical design intersects with microarchitecture, RTL, verification, design methodology, libraries/PDKs, and system-level PPA trade-offs
  • Strong communication and collaboration skills, with the ability to translate deep technical trade-offs clearly in customer-facing and cross-functional settings
  • Comfortable operating as a consultative expert and advisor - unblocking teams, shaping decisions, and raising technical quality without necessarily being the direct implementation owner
  • Strong scripting and automation skills in Python, Tcl, or similar
  • Excited to grow beyond domain SME responsibilities into a broader Forward Deployed Engineering role, including hands-on solution building, customer-facing delivery, and ownership of deployment outcomes

Preferred Qualifications
  • Experience working across multiple semiconductor companies, design environments, or tool stacks, with a point of view shaped by different engineering cultures and methodologies
  • Experience partnering with external customers, strategic accounts, or design partners in a technical advisory capacity
  • Experience defining or scaling evaluation workflows, benchmarks, or acceptance criteria
  • Exposure to adjacent workflows such as design and/or verification
  • Experience applying AI/LLM systems to semiconductor workflows
  • Prior experience in solutions engineering, field engineering, customer-facing technical delivery, or consultative technical roles

Compensation Range: $162K - $302K USD
About OpenAI
OpenAI is an AI research and deployment company dedicated to ensuring that general-purpose artificial intelligence benefits all of humanity. We push the boundaries of the capabilities of AI systems and seek to safely deploy them to the world through our products. AI is an extremely powerful tool that must be created with safety and human needs at its core, and to achieve our mission, we must encompass and value the many different perspectives, voices, and experiences that form the full spectrum of humanity.
We are an equal opportunity employer, and we do not discriminate on the basis of race, religion, color, national origin, sex, sexual orientation, age, veteran status, disability, genetic information, or other applicable legally protected characteristic.
For additional information, please see OpenAI's Affirmative Action and Equal Employment Opportunity Policy Statement.
Background checks for applicants will be administered in accordance with applicable law, and qualified applicants with arrest or conviction records will be considered for employment consistent with those laws, including the San Francisco Fair Chance Ordinance, the Los Angeles County Fair Chance Ordinance for Employers, and the California Fair Chance Act, for US-based candidates. For unincorporated Los Angeles County workers: we reasonably believe that criminal history may have a direct, adverse and negative relationship with the following job duties, potentially resulting in the withdrawal of a conditional offer of employment: protect computer hardware entrusted to you from theft, loss or damage; return all computer hardware in your possession (including the data contained therein) upon termination of employment or end of assignment; and maintain the confidentiality of proprietary, confidential, and non-public information. In addition, job duties require access to secure and protected information technology systems and related data security obligations.
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