Digital IC Design Engineer Intern
South San Francisco, CA · On-site
$35/hr
Team Description: The Brain Interfaces Soc Department delivers chip architecture and silicon ... Temporary Employees & Interns excluded
South San Francisco, CA · On-site
$35/hr
Team Description: The Brain Interfaces Soc Department delivers chip architecture and silicon ... Temporary Employees & Interns excluded
South San Francisco, CA · On-site
$35/hr
Team Description: The Brain Interfaces Soc Department delivers chip architecture and silicon ... Temporary Employees & Interns excluded
South San Francisco, CA · On-site
$125K - $291K/yr
Team Description: The Brain Interfaces SoC Department delivers chip architecture and silicon ... Temporary Employees & Interns excluded
South San Francisco, CA · On-site
$125K - $291K/yr
Team Description: The Brain Interfaces SoC Department delivers chip architecture and silicon ... Temporary Employees & Interns excluded
Team Description: The Brain Interfaces Soc Department delivers chip architecture and silicon ... Temporary Employees & Interns excluded
Team Description: The Brain Interfaces Soc Department delivers chip architecture and silicon ... Temporary Employees & Interns excluded
South San Francisco, CA · On-site
$83K - $139K/yr
... chip design with advanced architectures and hardware accelerators with a goal of enhancing the ... Temporary Employees & Interns excluded
South San Francisco, CA · On-site
$83K - $139K/yr
... chip design with advanced architectures and hardware accelerators with a goal of enhancing the ... Temporary Employees & Interns excluded
South San Francisco, CA · On-site
$123 - $216/hr
Build and maintain scalable EDA compute infrastructure for analog and digital chip design * Develop ... Temporary Employees & Interns excluded #J-18808-Ljbffr
South San Francisco, CA · On-site
$123 - $216/hr
Build and maintain scalable EDA compute infrastructure for analog and digital chip design * Develop ... Temporary Employees & Interns excluded #J-18808-Ljbffr
Austin, TX · On-site
$116K - $233K/yr
Team Description: The Brain Interfaces Soc Department delivers chip architecture and silicon ... Temporary Employees & Interns excluded
Austin, TX · On-site
$116K - $233K/yr
Team Description: The Brain Interfaces Soc Department delivers chip architecture and silicon ... Temporary Employees & Interns excluded
Austin, TX · On-site
$151K - $261K/yr
Team Description: The Brain Interfaces Soc Department delivers chip architecture and silicon ... Temporary Employees & Interns excluded
Austin, TX · On-site
$151K - $261K/yr
Team Description: The Brain Interfaces Soc Department delivers chip architecture and silicon ... Temporary Employees & Interns excluded
Austin, TX · On-site
$151 - $261/hr
Team Description The Brain Interfaces Soc Department delivers chip architecture and silicon ... Temporary Employees & Interns excluded #J-18808-Ljbffr
Austin, TX · On-site
$151 - $261/hr
Team Description The Brain Interfaces Soc Department delivers chip architecture and silicon ... Temporary Employees & Interns excluded #J-18808-Ljbffr
Bodega Bay, CA · On-site
$230K - $322K/yr
A temporary remote work exception is approved while our Bay Area and San Diego sites are being ... Design and simulate on-chip electromagnetic (EM) structures and collaborate with the package ...
Bodega Bay, CA · On-site
$230K - $322K/yr
A temporary remote work exception is approved while our Bay Area and San Diego sites are being ... Design and simulate on-chip electromagnetic (EM) structures and collaborate with the package ...
San Diego, CA · On-site
$230K - $322K/yr
A temporary remote work exception is approved while our Bay Area and San Diego sites are being ... Design and simulate on-chip electromagnetic (EM) structures and collaborate with the package ...
San Diego, CA · On-site
$230K - $322K/yr
A temporary remote work exception is approved while our Bay Area and San Diego sites are being ... Design and simulate on-chip electromagnetic (EM) structures and collaborate with the package ...
Seattle, WA · On-site
$230K - $322K/yr
A temporary remote work exception is approved while our Bay Area and San Diego sites are being ... Design and simulate on-chip electromagnetic (EM) structures and collaborate with the package ...
Seattle, WA · On-site
$230K - $322K/yr
A temporary remote work exception is approved while our Bay Area and San Diego sites are being ... Design and simulate on-chip electromagnetic (EM) structures and collaborate with the package ...
Seattle, WA · On-site
$230K - $322K/yr
A temporary remote work exception is approved while our Bay Area and San Diego sites are being ... Design and simulate on-chip electromagnetic (EM) structures and collaborate with the package ...
Seattle, WA · On-site
$230K - $322K/yr
A temporary remote work exception is approved while our Bay Area and San Diego sites are being ... Design and simulate on-chip electromagnetic (EM) structures and collaborate with the package ...
Temp-to-Perm Location: Manassas, VA Clearance: Ability to obtain a Department of Defense Secret ... Understanding of System-On-Chip (SoC) design with embedded processor on FPGA * Ability to perform ...
Temp-to-Perm Location: Manassas, VA Clearance: Ability to obtain a Department of Defense Secret ... Understanding of System-On-Chip (SoC) design with embedded processor on FPGA * Ability to perform ...
Temp-to-Perm Location: Manassas, VA Clearance: Ability to obtain a Department of Defense Secret ... Understanding of System-On-Chip (SoC) design with embedded processor on FPGA * Ability to perform ...
Temp-to-Perm Location: Manassas, VA Clearance: Ability to obtain a Department of Defense Secret ... Understanding of System-On-Chip (SoC) design with embedded processor on FPGA * Ability to perform ...
South San Francisco, CA · On-site
$123K - $216K/yr
Build and maintain scalable EDA compute infrastructure for analog and digital chip design * Develop ... Temporary Employees & Interns excluded
South San Francisco, CA · On-site
$123K - $216K/yr
Build and maintain scalable EDA compute infrastructure for analog and digital chip design * Develop ... Temporary Employees & Interns excluded
Manassas, VA · On-site
$67/hr
Temp-to-Perm Location: Manassas, VA Clearance: Ability to obtain a Department of Defense Secret ... Understanding of System-On-Chip (SoC) design with embedded processor on FPGA * Ability to perform ...
Manassas, VA · On-site
$67/hr
Temp-to-Perm Location: Manassas, VA Clearance: Ability to obtain a Department of Defense Secret ... Understanding of System-On-Chip (SoC) design with embedded processor on FPGA * Ability to perform ...
Temporary Part-Time Location: Glassboro, New Jersey Categories: Faculty - Henry M. Rowan College of ... VLSI design, chip design, advanced chip manufacturing, solid-state systems * Control systems,
Temporary Part-Time Location: Glassboro, New Jersey Categories: Faculty - Henry M. Rowan College of ... VLSI design, chip design, advanced chip manufacturing, solid-state systems * Control systems,
Temporary Part-Time Location: Glassboro, New Jersey Categories: Faculty - Henry M. Rowan College of ... VLSI design, chip design, advanced chip manufacturing, solid-state systems * Control systems,
Temporary Part-Time Location: Glassboro, New Jersey Categories: Faculty - Henry M. Rowan College of ... VLSI design, chip design, advanced chip manufacturing, solid-state systems * Control systems,
South San Francisco, CA · On-site
$131 - $243/hr
... CPU, ASIC design and verification fundamentals to work in Neuralink's System-on-Chip (SoC ... Temporary Employees & Interns excluded #J-18808-Ljbffr
South San Francisco, CA · On-site
$131 - $243/hr
... CPU, ASIC design and verification fundamentals to work in Neuralink's System-on-Chip (SoC ... Temporary Employees & Interns excluded #J-18808-Ljbffr
South San Francisco, CA · On-site
$131K - $243K/yr
... CPU, ASIC design and verification fundamentals to work in Neuralink's System-on-Chip (SoC ... Temporary Employees & Interns excluded
South San Francisco, CA · On-site
$131K - $243K/yr
... CPU, ASIC design and verification fundamentals to work in Neuralink's System-on-Chip (SoC ... Temporary Employees & Interns excluded
$45K - $57.8K
4% of jobs
$57.8K - $70.5K
2% of jobs
$70.5K - $83.3K
12% of jobs
$93.7K is the 25th percentile. Wages below this are outliers.
$83.3K - $96.1K
9% of jobs
$96.1K - $108.9K
11% of jobs
The median wage is $120.7K / yr.
$108.9K - $121.6K
14% of jobs
$121.6K - $134.4K
22% of jobs
$136.8K is the 75th percentile. Wages above this are outliers.
$134.4K - $147.2K
9% of jobs
$147.2K - $160K
9% of jobs
$160K - $172.7K
3% of jobs
$172.7K - $185.5K
6% of jobs
$45K
$120.8K
$185.5K
| Aspect | Temporary Chip Design | Contract Chip Design |
|---|---|---|
| Credentials | Typically requires a degree in Electrical Engineering or Computer Engineering, with some certifications preferred | Similar credentials, often with additional certifications in FPGA or ASIC design |
| Work Environment | Usually in-house or on-site at a company's facility for a limited period | Often remote or on-site, working for a consulting firm or as an independent contractor |
| Employer & Industry Usage | Used by companies to fill short-term design needs within their organization | Used by firms to provide specialized design services on a project basis |
Temporary Chip Design involves short-term in-house roles within a company, focusing on specific projects. Contract Chip Design typically refers to external consultants or firms providing design services for a set period. Both roles require similar skills and credentials but differ mainly in employment type and work setting.
Cities with the most Temporary Chip Design job openings:
The most popular types of Chip Design jobs are:
States with the most job openings for Temporary Chip Design jobs include:
The top searched job categories for Temporary Chip Design jobs are:

$35/hr
Full-time, Internship
Medical, Dental, Vision, Retirement
Re-posted 28 days ago
Sourced by ZipRecruiter
Biotechnology research and development
201 - 500 Employees
San Francisco, CA, US
2016