Build Verilog/Verilog-a models for analog circuit blocks to enable efficient simulations at chip ... USD 32.30 - 58.32 per hour Thank you for your interest in our temporary position. Please be advised ...
Build Verilog/Verilog-a models for analog circuit blocks to enable efficient simulations at chip ... USD 32.30 - 58.32 per hour Thank you for your interest in our temporary position. Please be advised ...
Build Verilog/Verilog-a models for analog circuit blocks to enable efficient simulations at chip ... USD 32.30 - 58.32 per hour Thank you for your interest in our temporary position. Please be advised ...
Build Verilog/Verilog-a models for analog circuit blocks to enable efficient simulations at chip ... USD 32.30 - 58.32 per hour Thank you for your interest in our temporary position. Please be advised ...
Build Verilog/Verilog-a models for analog circuit blocks to enable efficient simulations at chip ... USD 32.30 - 58.32 per hour Thank you for your interest in our temporary position. Please be advised ...
Build Verilog/Verilog-a models for analog circuit blocks to enable efficient simulations at chip ... USD 32.30 - 58.32 per hour Thank you for your interest in our temporary position. Please be advised ...
Signal Processing Engineer
Austin, TX ยท On-site
$121K - $230.50K/yr
Collaborate with the digital design team to define micro-architectures for custom on-chip ... Temporary Employees & Interns excluded
Signal Processing Engineer
Austin, TX ยท On-site
$121K - $230.50K/yr
Collaborate with the digital design team to define micro-architectures for custom on-chip ... Temporary Employees & Interns excluded
Principal mmWave-RFIC Engineer
$197.53K - $276.54K/yr
A temporary remote work exception is approved while our Bay Area and San Diego sites are being ... Design and simulate on-chip electromagnetic (EM) structures and collaborate with the package ...
Principal mmWave-RFIC Engineer
$197.53K - $276.54K/yr
A temporary remote work exception is approved while our Bay Area and San Diego sites are being ... Design and simulate on-chip electromagnetic (EM) structures and collaborate with the package ...
Principal mmWave-RFIC Engineer
$197.53K - $276.54K/yr
A temporary remote work exception is approved while our Bay Area and San Diego sites are being ... Design and simulate on-chip electromagnetic (EM) structures and collaborate with the package ...
Principal mmWave-RFIC Engineer
$197.53K - $276.54K/yr
A temporary remote work exception is approved while our Bay Area and San Diego sites are being ... Design and simulate on-chip electromagnetic (EM) structures and collaborate with the package ...
Principal mmWave-RFIC Engineer
$197.53K - $276.54K/yr
A temporary remote work exception is approved while our Bay Area and San Diego sites are being ... Design and simulate on-chip electromagnetic (EM) structures and collaborate with the package ...
Principal mmWave-RFIC Engineer
$197.53K - $276.54K/yr
A temporary remote work exception is approved while our Bay Area and San Diego sites are being ... Design and simulate on-chip electromagnetic (EM) structures and collaborate with the package ...
Essential Duties and Responsibilities: โข Design and simulate circuits at transistor-level to ... chip architectures and designs โข Independently drive solutions to complex problems - develop ...
Essential Duties and Responsibilities: โข Design and simulate circuits at transistor-level to ... chip architectures and designs โข Independently drive solutions to complex problems - develop ...
Embedded Software Engineer, Implant Embedded Systems
Austin, TX ยท On-site
$119K - $281K/yr
You will have the opportunity to work closely with chip designers, electrical engineers, and ... Ability to design bare-metal embedded systems in highly constrained environments * Strong ...
Embedded Software Engineer, Implant Embedded Systems
Austin, TX ยท On-site
$119K - $281K/yr
You will have the opportunity to work closely with chip designers, electrical engineers, and ... Ability to design bare-metal embedded systems in highly constrained environments * Strong ...
Principal mmWave-RFIC Engineer
Seattle, WA ยท On-site
$197.53K - $276.54K/yr
A temporary remote work exception is approved while our Bay Area and San Diego sites are being ... Design and simulate on-chip electromagnetic (EM) structures and collaborate with the package ...
Principal mmWave-RFIC Engineer
Seattle, WA ยท On-site
$197.53K - $276.54K/yr
A temporary remote work exception is approved while our Bay Area and San Diego sites are being ... Design and simulate on-chip electromagnetic (EM) structures and collaborate with the package ...
Manufacturing Technician
Austin, TX ยท On-site
$25 - $31/hr
The Brain Interfaces Mechanical Engineering Team is responsible for the design, build, and testing ... You will be engaged with many day-to-day responsibilities, including flip-chip bonding, part ...
Manufacturing Technician
Austin, TX ยท On-site
$25 - $31/hr
The Brain Interfaces Mechanical Engineering Team is responsible for the design, build, and testing ... You will be engaged with many day-to-day responsibilities, including flip-chip bonding, part ...
Distinguished Engineer, ASIC (CONTRACT)
Burlington, MA ยท On-site +1
$180.60K/yr
... design, implement, and verify digital signal processing, high speed interface, and system-on-a-chip ... Burlington, MA For this temporary role, we are only considering candidates who are legally ...
Distinguished Engineer, ASIC (CONTRACT)
Burlington, MA ยท On-site +1
$180.60K/yr
... design, implement, and verify digital signal processing, high speed interface, and system-on-a-chip ... Burlington, MA For this temporary role, we are only considering candidates who are legally ...
... design, implement, and verify digital signal processing, high speed interface, and system-on-a-chip ... Burlington, MA For this temporary role, we are only considering candidates who are legally ...
New
Quick apply
... design, implement, and verify digital signal processing, high speed interface, and system-on-a-chip ... Burlington, MA For this temporary role, we are only considering candidates who are legally ...
New
Senior IO Validation Engineer
Santa Clara, CA ยท Hybrid
$122.70K - $168.50K/yr
Contribute to design of next generation of high-speed IOs, including NVLink and NVLink-C2C ... HSIOs like PCIE or chip-to-chip interconnects including understanding of process/temp/voltage ...
Senior IO Validation Engineer
Santa Clara, CA ยท Hybrid
$122.70K - $168.50K/yr
Contribute to design of next generation of high-speed IOs, including NVLink and NVLink-C2C ... HSIOs like PCIE or chip-to-chip interconnects including understanding of process/temp/voltage ...
Senior IO Validation Engineer
Santa Clara, CA ยท On-site
$122.70K - $168.50K/yr
Contribute to design of next generation of high-speed IOs, including NVLink and NVLink-C2C ... HSIOs like PCIE or chip-to-chip interconnects including understanding of process/temp/voltage ...
Senior IO Validation Engineer
Santa Clara, CA ยท On-site
$122.70K - $168.50K/yr
Contribute to design of next generation of high-speed IOs, including NVLink and NVLink-C2C ... HSIOs like PCIE or chip-to-chip interconnects including understanding of process/temp/voltage ...
Hardware Validation Engineer
Santa Clara, CA ยท Hybrid
$145K - $191.40K/yr
... design. * Working experience in a few of the following areas: * HSIOs like PCIE or chip-to-chip interconnects including understanding of process/temp/voltage sensitivity on BER. * Broad exposure to a ...
Hardware Validation Engineer
Santa Clara, CA ยท Hybrid
$145K - $191.40K/yr
... design. * Working experience in a few of the following areas: * HSIOs like PCIE or chip-to-chip interconnects including understanding of process/temp/voltage sensitivity on BER. * Broad exposure to a ...
Hardware Validation Engineer
Santa Clara, CA ยท On-site
$145K - $191.40K/yr
... design. * Working experience in a few of the following areas: * HSIOs like PCIE or chip-to-chip interconnects including understanding of process/temp/voltage sensitivity on BER. * Broad exposure to a ...
Hardware Validation Engineer
Santa Clara, CA ยท On-site
$145K - $191.40K/yr
... design. * Working experience in a few of the following areas: * HSIOs like PCIE or chip-to-chip interconnects including understanding of process/temp/voltage sensitivity on BER. * Broad exposure to a ...
Electrical Engineer Intern, Implant Embedded Systems
Austin, TX ยท On-site
$35/hr
... design, layout, and bring-up) as well as collaborating closely with chip designers, firmware ... Temporary Employees & Interns excluded
Electrical Engineer Intern, Implant Embedded Systems
Austin, TX ยท On-site
$35/hr
... design, layout, and bring-up) as well as collaborating closely with chip designers, firmware ... Temporary Employees & Interns excluded
Principal IC Package Design Engineer - TeraWave
$230.77K - $323.08K/yr
A temporary remote work exception is approved while our Bay Area and San Diego sites are being ... Knowledge of System in Package (SiP), Antenna in Package (AiP), and Multi-Chip Module (MCM ...
Principal IC Package Design Engineer - TeraWave
$230.77K - $323.08K/yr
A temporary remote work exception is approved while our Bay Area and San Diego sites are being ... Knowledge of System in Package (SiP), Antenna in Package (AiP), and Multi-Chip Module (MCM ...
Principal IC Package Design Engineer - TeraWave
$230.77K - $323.08K/yr
A temporary remote work exception is approved while our Bay Area and San Diego sites are being ... Knowledge of System in Package (SiP), Antenna in Package (AiP), and Multi-Chip Module (MCM ...
Principal IC Package Design Engineer - TeraWave
$230.77K - $323.08K/yr
A temporary remote work exception is approved while our Bay Area and San Diego sites are being ... Knowledge of System in Package (SiP), Antenna in Package (AiP), and Multi-Chip Module (MCM ...
Temporary Chip Design information
See salary details
$45K - $57.8K
4% of jobs
$57.8K - $70.5K
2% of jobs
$70.5K - $83.3K
12% of jobs
$93.7K is the 25th percentile. Wages below this are outliers.
$83.3K - $96.1K
9% of jobs
$96.1K - $108.9K
11% of jobs
The median wage is $120.7K / yr.
$108.9K - $121.6K
14% of jobs
$121.6K - $134.4K
22% of jobs
$136.8K is the 75th percentile. Wages above this are outliers.
$134.4K - $147.2K
9% of jobs
$147.2K - $160K
9% of jobs
$160K - $172.7K
3% of jobs
$172.7K - $185.5K
6% of jobs
$45K
$120.8K
$185.5K
How much do temporary chip design jobs pay per year?
What is the difference between Temporary Chip Design vs Contract Chip Design?
| Aspect | Temporary Chip Design | Contract Chip Design |
|---|---|---|
| Credentials | Typically requires a degree in Electrical Engineering or Computer Engineering, with some certifications preferred | Similar credentials, often with additional certifications in FPGA or ASIC design |
| Work Environment | Usually in-house or on-site at a company's facility for a limited period | Often remote or on-site, working for a consulting firm or as an independent contractor |
| Employer & Industry Usage | Used by companies to fill short-term design needs within their organization | Used by firms to provide specialized design services on a project basis |
Temporary Chip Design involves short-term in-house roles within a company, focusing on specific projects. Contract Chip Design typically refers to external consultants or firms providing design services for a set period. Both roles require similar skills and credentials but differ mainly in employment type and work setting.

Intern, Analog IC design, Technology Platforms - Summer 2026
Murata AmericasSan Diego, CA โข On-site
Temporary, Internship
Posted 26 days ago
Job description
Job Summary
The Analog Design Intern will assist engineers in designing and developing Technology Platforms' analog circuits which form a critical part of pSemi's RFIC products for cellular and connectivity applications. The analog circuits may include but are not limited to charge pumps, bandgap references, low drop-out regulators, logic translators, RF gate drivers, power-on-reset, DFT circuit blocks, etc. Additionally, the candidate will support development of veriloga models for the various analog circuit blocks as well as help document design information for circuit blocks. The candidate may need to interface with Digital design, Layout, Process technology and Modeling teams as necessitated by the scope of their assigned project.
Roles & Responsibilities
- Analog/Mixed-Signal Block Design: Work independently and with our engineers on simulation and layout of circuit blocks.
- IP Block Characterization: Work with Characterization engineer to analyze data from circuit block level testing and create test reports.
- Product Support: Build Verilog/Verilog-a models for analog circuit blocks to enable efficient simulations at chip level. Interface with Analog and RFIC design teams as needed to fine tune the models
- Documentation: Document any design work to educate others on IP block usage.
Minimum Qualifications
- Knowledge of analog integrated circuit design
- Software tools: Cadence, Excel
- Strength in documentation clarity and completeness
- Able to work effectively within the group and cross-functionally with other teams
- Strong sense of urgency to meet task requirements on schedule
Preferred Qualifications
- Familiarity with RF IC and Systems topics
- Familiarity with SOI process
Education & Experience Requirements
- BSEE or similar
- Enrolled in a MS or PhD EE program with RF/Mixed-Signal/Analog circuit focus
Work Environment
This job operates in a professional office environment. This role routinely uses standard office equipment.
Physical Demands
The physical demands described here are representative of those that must be met by an employee to successfully perform the essential functions of this job. While performing the duties of this job, the employee is regularly required to talk or hear. The employee frequently is required to stand; walk; use hands to finger, handle or feel; and reach with hands and arms. Specific vision abilities required by this job include close vision, distance vision, color vision, peripheral vision, depth perception and ability to adjust focus. This position requires the ability to occasionally lift office products and supplies, up to 20 pounds.
USD 32.30 - 58.32 per hour
Thank you for your interest in our temporary position. Please be advised that the selected candidate will be employed and receive all wages directly from a third-party staffing agency selected by pSemi.
pSemi Corporation supports a diverse workforce and is committed to a policy of equal employment opportunity for applicants and employees. pSemi does not discriminate on the basis of age, race, color, religion (including religious dress and grooming practices), sex/gender (including pregnancy, childbirth, or related medical conditions or breastfeeding), gender identity, gender expression, genetic information, national origin (including language use restrictions and possession of a driver's license issued under Vehicle Code section 12801.9), ancestry, physical or mental disability, legally-protected medical condition, military or veteran status (including "protected veterans" under applicable affirmative action laws), marital status, sexual orientation, or any other basis protected by local, state or federal laws applicable to the Company. pSemi also prohibits discrimination based on the perception that an employee or applicant has any of those characteristics, or is associated with a person who has or is perceived as having any of those characteristics.
Note: The Peregrine Semiconductor name, Peregrine Semiconductor logo and UltraCMOS are registered trademarks and the pSemi name, pSemi logo, HaRP and DuNE are trademarks of pSemi Corporation in the U.S. and other countries. All other trademarks are the property of their respective companies. pSemi products are protected under one or more of the following U.S. Patents: http://patents.psemi.com
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