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Chip Design Engineer Jobs in Arizona (NOW HIRING)

RF SoC System Timing Design And Validation Engineer Job Responsibilities ... Help guide chip design for proper system timing and synchronization of the interactions between ...

Physical Design Engineer

Phoenix, AZ · On-site

$135K - $139K/yr

Python Programming Language - * Physical Design Develop & own physical design implementation of ... Exp. in Block-level & Full-chip floor-planning & power grid planning,w/Python, TCL,or Perl progr ...

As a Principal Design Engineer located in Scottsdale, Arizona, you will have the opportunity to ... Chip layout experience for protection devices is desirable * Experience with Cadence environment ...

As a Principal Design Engineer located in Scottsdale, Arizona, you will have the opportunity to ... Chip layout experience for protection devices is desirable * Experience with Cadence environment ...

Analog Design Engineer

Phoenix, AZ · On-site

$200K/yr

The Hard IP and Test Chip Development team, within Intel's Central Engineering Group, is ... As an Analog Design Engineer at Intel, you will play a pivotal role in developing cutting-edge ...

The Hard IP and Test Chip Development team, within Intel's Central Engineering Group, is ... As an Analog Design Engineer at Intel, you will play a pivotal role in developing cutting-edge ...

Analog Design Engineer

Chandler, AZ · On-site

$198K/yr

Simulate and verify circuit and chip-level performance using Spectre and mixed-signal methodologies ... Engineering, or related field: * Bachelor's with 2+ years of relevant IC design experience.

Develops the logic design, register transfer level (RTL) coding, and simulation for a CPU required ... chip designs. Participates actively in the definition of architecture and microarchitecture ...

Digital Design Engineer

Chandler, AZ · On-site

$133K/yr

In this role, you will contribute to the design of system-on-chip (SoC) devices, digital signal ... Degree in Electrical Engineering, Computer Engineering, or a related technical field. * Bachelor ...

Principal Digital Design Engineer

Chandler, AZ · On-site +1

$200K - $250K/yr

Lead block- and chip-level integration, resolving interface and system issues * Ensure designs are ... engineering, Computer Engineering, or related field * 10+ years of experience in digital design ...

The Hard IP and Test Chip Development team, within Intel's Central Engineering Group, is ... We are seeking an experienced Senior Analog Design Engineer to join our engineering team. The ...

Staff Analog Design Engineer

Chandler, AZ · On-site

$198K/yr

Simulate and verify circuit and chip-level performance using Spectre and mixed-signal methodologies ... Engineering, or related field: * Bachelor's with 7+ years of relevant IC design experience.

Senior Analog Design Engineer

Chandler, AZ · On-site

$198K/yr

Simulate and verify circuit and chip-level performance using Spectre and mixed-signal methodologies ... Engineering, or related field: * Bachelor's with 5+ years of relevant IC design experience.

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Chip Design Engineer information

See Arizona salary details

$37.7K

$82.1K

$147.7K

How much do chip design engineer jobs pay per year?

As of Jun 15, 2026, the average yearly pay for chip design engineer in Arizona is $82,145.00, according to ZipRecruiter salary data. Most workers in this role earn between $63,400.00 and $91,800.00 per year, depending on experience, location, and employer.

What are some typical projects or daily tasks for a Chip Design Engineer?

As a Chip Design Engineer, your daily tasks often include designing and simulating integrated circuits, reviewing schematics, writing and verifying code in hardware description languages, and collaborating closely with layout engineers and verification teams. You may also participate in design reviews, troubleshoot potential issues, and optimize chip performance to meet specific requirements. Working with cross-functional teams, including software engineers and product managers, is common to ensure the chip integrates seamlessly with end products. This role provides opportunities to see your designs progress from concept to final manufacturing, offering valuable hands-on experience at each stage of development.

What are the key skills and qualifications needed to thrive in the Chip Design Engineer position, and why are they important?

To thrive as a Chip Design Engineer, you need a solid background in electrical engineering, digital and analog circuit design, and experience with VLSI principles, usually backed by a relevant degree. Proficiency with industry-standard tools like Cadence, Synopsys, and experience in HDL languages (such as Verilog or VHDL) is highly valued, as are certifications like Certified IC Designer. Strong problem-solving abilities, attention to detail, and effective teamwork and communication skills help set you apart. These competencies are critical for developing reliable, high-performance chips in a collaborative and deadline-driven environment.

What is a Chip Design Engineer job?

A Chip Design Engineer is responsible for designing and developing integrated circuits (ICs) used in electronic devices. They work with hardware description languages (HDLs) like Verilog or VHDL to create digital or analog circuit designs. Their role includes logic design, verification, simulation, and testing to ensure performance and power efficiency. They collaborate with teams across hardware, software, and manufacturing to bring chips from concept to production. Chip Design Engineers are essential in industries like consumer electronics, automotive, and telecommunications.

What cities in Arizona are hiring for Chip Design Engineer jobs? Cities in Arizona with the most Chip Design Engineer job openings:
RF SoC Design Engineer

RF SoC Design Engineer

Alphacore Inc

Tempe, AZ • On-site

Full-time

Posted 21 hours ago


Job description

RF SoC System Timing Design And Validation Engineer
Job Responsibilities:
Help guide chip design for proper system timing and synchronization of the interactions between system components such as PLL, DAC, ADC, and on-chip digital post-processing of ADC outputs. Digital post-processing will include down-sampling and decimation filter structures. Some examples of the synchronization that will be required are below:
1) Coarse alignment of 32 clock phases that are generated from single master clock. These clock phases drive 32 ADC channels that feed the digital post-processing.
2) The digital post-processing filters fed by the 32 ADC channel outputs will be highly parallelized. The final output will be a down-sampled and decimated stream of data originating from the 32 ADC channels. Design and verification of the synchronization of the parallelized digital processing blocks is needed.
3) Synchronization of all enable signals for the RFSoC subsystems: PLL, DAC, ADC, calibration engines for the ADC subsystem, and digital post-processing.
Desired Experience:
- Knowledge of synchronization procedures and capabilities with synchronization tools for RFSoC systems
- Experience using Cadence design tools especially tools used for RFSoC timing such as Tempus Timing Signoff Solution and Quantus Extraction Solution. Experience with comparable tools from other vendors such as Synopsys is also acceptable, but final validation of all projects will use Cadence vendor tools.
- 3+ years of RFSoC design with focus on system timing and validation
- Multi-Tile Synchronization for multiple channels of DAC and ADC for phased array applications
- Clock distribution of a common clock within an RFSoC system and eventually across multiple RFSoC systems