Memory array/IP design, memory circuit innovation, test-chip design. * Pre-Si verification, post-Si ... PhD with 1-2 years of professional experience gained through either internships or full-time ...
Memory array/IP design, memory circuit innovation, test-chip design. * Pre-Si verification, post-Si ... PhD with 1-2 years of professional experience gained through either internships or full-time ...
Intern Program - Engineering Pathways
Chandler, AZ · Hybrid
$16.50 - $21.50/hr
Internships span several areas, with some projects crossing more than one: Hardware & Chip Design -- Work with digital logic, RTL, FPGA, circuits, physical design or semiconductor technology. Testing ...
Intern Program - Engineering Pathways
Chandler, AZ · Hybrid
$16.50 - $21.50/hr
Internships span several areas, with some projects crossing more than one: Hardware & Chip Design -- Work with digital logic, RTL, FPGA, circuits, physical design or semiconductor technology. Testing ...
SOC Physical Design Static Timing Analysis Engineer
Phoenix, AZ · On-site
$164K - $311K/yr
Generate and verify timing constraints while addressing timing violations at the chip or block ... internship experiences and or schoolwork/classes/research. Minimum Qualifications * Bachelor ...
SOC Physical Design Static Timing Analysis Engineer
Phoenix, AZ · On-site
$164K - $311K/yr
Generate and verify timing constraints while addressing timing violations at the chip or block ... internship experiences and or schoolwork/classes/research. Minimum Qualifications * Bachelor ...
SOC Physical Design Static Timing Analysis Engineer
Phoenix, AZ · On-site
$164K - $311K/yr
Generate and verify timing constraints while addressing timing violations at the chip or block ... internship experiences and or schoolwork/classes/research. Minimum Qualifications * Bachelor ...
SOC Physical Design Static Timing Analysis Engineer
Phoenix, AZ · On-site
$164K - $311K/yr
Generate and verify timing constraints while addressing timing violations at the chip or block ... internship experiences and or schoolwork/classes/research. Minimum Qualifications * Bachelor ...
Graduate Program - Engineering Pathways
Chandler, AZ · On-site
$119K - $161K/yr
Hardware & Chip Design -- Design Arm technology through digital logic, RTL, FPGA, circuits ... Relevant experience can come from coursework, research, internships, placements, personal projects ...
Graduate Program - Engineering Pathways
Chandler, AZ · On-site
$119K - $161K/yr
Hardware & Chip Design -- Design Arm technology through digital logic, RTL, FPGA, circuits ... Relevant experience can come from coursework, research, internships, placements, personal projects ...
CPU RTL Design Engineer
$141K - $269K/yr
... into full-chip designs. Your expertise will be pivotal in defining architecture and ... internship experiences. Minimum Qualifications: Bachelor's degree in electrical engineering ...
CPU RTL Design Engineer
$141K - $269K/yr
... into full-chip designs. Your expertise will be pivotal in defining architecture and ... internship experiences. Minimum Qualifications: Bachelor's degree in electrical engineering ...
Undergraduate Intern at Intel Phoenix, AZ
Phoenix, AZ · On-site
$60 - $80/hr
... chip manufacturer, Intel strives to make every facet of semiconductor manufacturing ... design, development, manufacturing, and assembly/test facilities, all focused on utilizing the ...
Undergraduate Intern at Intel Phoenix, AZ
Phoenix, AZ · On-site
$60 - $80/hr
... chip manufacturer, Intel strives to make every facet of semiconductor manufacturing ... design, development, manufacturing, and assembly/test facilities, all focused on utilizing the ...
DFT Application Engineer
Phoenix, AZ · On-site
... experience, internship experience and / or schoolwork/classes/research. The preferred ... design block level and full chip level, including ATPG validation and DFT timing/signoff at SOC ...
DFT Application Engineer
Phoenix, AZ · On-site
... experience, internship experience and / or schoolwork/classes/research. The preferred ... design block level and full chip level, including ATPG validation and DFT timing/signoff at SOC ...
... experience, internship experience and / or schoolwork/classes/research. The preferred ... design block level and full chip level, including ATPG validation and DFT timing/signoff at SOC ...
... experience, internship experience and / or schoolwork/classes/research. The preferred ... design block level and full chip level, including ATPG validation and DFT timing/signoff at SOC ...
Join Intel, the world's leading semiconductor manufacturer, as we push the boundaries of chip ... Analyze stakeholder requirements to identify key challenges and design optimal application/system ...
Join Intel, the world's leading semiconductor manufacturer, as we push the boundaries of chip ... Analyze stakeholder requirements to identify key challenges and design optimal application/system ...
Join Intel, the world's leading semiconductor manufacturer, as we push the boundaries of chip ... Analyze stakeholder requirements to identify key challenges and design optimal application/system ...
Join Intel, the world's leading semiconductor manufacturer, as we push the boundaries of chip ... Analyze stakeholder requirements to identify key challenges and design optimal application/system ...
Advanced Packaging Intern, MS - Summer 2027
Chandler, AZ · On-site
$16.25 - $21/hr
Many of the new designs require multi-chip and multiple component configurations with high-speed IP ... Collaborate with package design, layout, hardware, and IP teams to optimize electrical performance.
New
Advanced Packaging Intern, MS - Summer 2027
Chandler, AZ · On-site
$16.25 - $21/hr
Many of the new designs require multi-chip and multiple component configurations with high-speed IP ... Collaborate with package design, layout, hardware, and IP teams to optimize electrical performance.
New
Advanced Packaging Intern, MS - Summer 2027
Chandler, AZ · On-site
$16.50 - $21.50/hr
Many of the new designs require multi-chip and multiple component configurations with high-speed IP ... Collaborate with package design, layout, hardware, and IP teams to optimize electrical performance.
New
Advanced Packaging Intern, MS - Summer 2027
Chandler, AZ · On-site
$16.50 - $21.50/hr
Many of the new designs require multi-chip and multiple component configurations with high-speed IP ... Collaborate with package design, layout, hardware, and IP teams to optimize electrical performance.
New
There are several positions available at all levels (even for recent grads with internship ... design and VHDL coding Four (4) years of experience with embedded processor and System on a Chip ...
There are several positions available at all levels (even for recent grads with internship ... design and VHDL coding Four (4) years of experience with embedded processor and System on a Chip ...
There are several positions available at all levels (even for recent grads with internship ... design and VHDL coding Four (4) years of experience with embedded processor and System on a Chip ...
There are several positions available at all levels (even for recent grads with internship ... design and VHDL coding Four (4) years of experience with embedded processor and System on a Chip ...
Intern (NPI Engineering)
Phoenix, AZ · On-site
$15.75 - $20.50/hr
We indirectly touch every semiconductor chip that goes into every smartphone, smart car, and device ... Prior internship, or project experience in a manufacturing or product design environment is an ...
Intern (NPI Engineering)
Phoenix, AZ · On-site
$15.75 - $20.50/hr
We indirectly touch every semiconductor chip that goes into every smartphone, smart car, and device ... Prior internship, or project experience in a manufacturing or product design environment is an ...
Intern (NPI Engineering)
Phoenix, AZ · On-site
$15.75 - $20.50/hr
We indirectly touch every semiconductor chip that goes into every smartphone, smart car, and device ... Prior internship, or project experience in a manufacturing or product design environment is an ...
Intern (NPI Engineering)
Phoenix, AZ · On-site
$15.75 - $20.50/hr
We indirectly touch every semiconductor chip that goes into every smartphone, smart car, and device ... Prior internship, or project experience in a manufacturing or product design environment is an ...
Intern (NPI Engineering)
$15.75 - $20.50/hr
We indirectly touch every semiconductor chip that goes into every smartphone, smart car, and device ... Prior internship, or project experience in a manufacturing or product design environment is an ...
Quick apply
Intern (NPI Engineering)
$15.75 - $20.50/hr
We indirectly touch every semiconductor chip that goes into every smartphone, smart car, and device ... Prior internship, or project experience in a manufacturing or product design environment is an ...
Metrology Engineering Technican
Phoenix, AZ · On-site
$60 - $80/hr
At our state-of-the-art facility in Arizona, we are building the future of chip manufacturing ... Design and develop relevant tooling and fixtures to support manufacturing operations * Partner with ...
Metrology Engineering Technican
Phoenix, AZ · On-site
$60 - $80/hr
At our state-of-the-art facility in Arizona, we are building the future of chip manufacturing ... Design and develop relevant tooling and fixtures to support manufacturing operations * Partner with ...
Design and develop relevant tooling and fixtures to support manufacturing operations * Partner with ... internship experience. This Position is not eligible for Intel immigration sponsorship. Minimum ...
Design and develop relevant tooling and fixtures to support manufacturing operations * Partner with ... internship experience. This Position is not eligible for Intel immigration sponsorship. Minimum ...
Internship Chip Design information
What is an internship in chip design?
What types of projects and responsibilities can I expect during an internship in chip design?
What are the key skills and qualifications needed to thrive as an internship chip design, and why are they important?
What is the difference between Internship Chip Design vs Chip Design Engineer?
| Aspect | Internship Chip Design | Chip Design Engineer |
|---|---|---|
| Required Credentials | Enrolled in or recent graduate of Electrical Engineering or related field | Bachelor's or Master's in Electrical Engineering, Computer Engineering, or related |
| Work Environment | Internship programs, team projects, supervised tasks | Full-time professional setting, independent project work |
| Employer & Industry Usage | Internship positions in semiconductor and electronics companies | Full-time roles in chip design companies, tech firms, or semiconductor industry |
| Comparison Search Intent | Learning about entry-level opportunities and training | Understanding professional career roles and responsibilities |
Internship Chip Design positions are entry-level opportunities aimed at students or recent graduates, focusing on training and skill development under supervision. Chip Design Engineers are full-time professionals responsible for designing, testing, and implementing integrated circuits independently. While internships provide foundational experience, engineers hold advanced responsibilities in the industry.
What are the most commonly searched types of Chip Design jobs in Arizona?
The most popular types of Chip Design jobs in Arizona are:
What are popular job titles related to Internship Chip Design jobs in Arizona?
For Internship Chip Design jobs in Arizona, the most frequently searched job titles are:
- Embedded Engineer
- Contract Embedded Software Engineer
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What job categories do people searching Internship Chip Design jobs in Arizona look for?
The top searched job categories for Internship Chip Design jobs in Arizona are:
What cities in Arizona are hiring for Internship Chip Design jobs?
Cities in Arizona with the most Internship Chip Design job openings:

Memory Circuit Design Engineer
Phoenix, AZ
Full-time
Medical, Retirement, PTO
Re-posted 16 days ago
Key responsibilities
Develop and optimize memory circuits, including pathfinding activities and PPA improvements through design technology co-optimization.
Design, layout, and automate memory bit-cell and complex periphery ICs, as well as memory array/IP design and test-chip development.
Perform pre-Si verification, post-Si validation, and debugging to enable yield and parametric tracking/ramp.
Intel rating
8.7
Based on 147 frontline employees who took The Breakroom Quiz
18th of 161 rated electronics manufacturers
Job description
The world is transforming - and so is Intel. Intel is a company of bold and curious inventors and problem solvers who create some of the most astounding technology advancements and experiences in the world. With a legacy of relentless innovation and a commitment to bring smart, connected devices to every person on Earth, our diverse and brilliant teams are continually searching for tomorrow's technology and revel in the challenge that changing the world for the better brings. We work every single day to design and manufacture silicon products that empower people's digital lives. Come join us and do something wonderful.
The Advanced Design (AD) team is part of Intel's larger Design Technology Platform (DTP) Organization and is focused on pathfinding and development of advanced memory technology. These circuits enable best-in-class memory collateral, IP and innovative product design across all generations of Intel process technology. At Intel, DTP is one of the key pillars enabling Intel to deliver winning products in the marketplace. Your work will directly enable Intel's internal and external customers to get to the market faster with products that include high-performance, high-density, low-power memory at the leading edge of the technology curve and implemented in Intel's advanced CMOS process technologies.
You will be partnering with and leveraging domain experts across various areas of technology development, EDA vendors and product design teams to develop and deliver high-quality industry-leading memory technology collaterals and to drive circuit innovations that enable next generation high-performance, high-density, low-power embedded memory designs on Intel advanced CMOS process technologies. In this position your responsibilities will include, but may not be limited to:
- Memory pathfinding activities and power, performance and area (PPA) optimization through design technology co-optimization (DTCO) and product design enablement.
- Memory bit-cell and complex periphery IC layout and automation.
- Memory array/IP design, memory circuit innovation, test-chip design.
- Pre-Si verification, post-Si validation and debugging to enable yield and parametric tracking/ramp.
You must possess the minimum qualifications listed below to interview for this position. Preferred qualifications are not required but may work to your advantage during the interview process.
Minimum Qualifications:
Master degree in Electrical Engineering, Computer Engineering, Electrical and Computer Engineering, or a related discipline, including 4+ years of professional experience gained through either internships or full-time employment Or a PhD in Electrical Engineering, Computer Engineering, Electrical and Computer Engineering, or a related discipline.
Technical Experience:
- Design, characterization, and verification of custom memory circuits such as SRAM, Register Files or ROM.
- Design trade-offs between power, performance, and area (PPA).
- Custom digital circuit design, simulation, layout design, and verification.
- Knowledge of EDA tools used for custom digital and memory circuit design.
Preferred Qualifications:
- PhD with 1-2 years of professional experience gained through either internships or full-time employment.
- Design technology co-optimization (DTCO).
- Post-Si validation experience.
- Knowledge of the CMOS ASIC design flow.
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.
Annual Salary Range for jobs which could be performed in the US: $122,440.00-232,190.00 USDThe range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.*
ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.About Intel
Sourced by ZipRecruiter
Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore's Law to bring smart, connected devices to every person on Earth
Industry
Manufacturing
Company size
10,000+ Employees
Headquarters location
Santa Clara, CA, US
Year founded
1968