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Google Asic Design Engineer Jobs in Minnesota (NOW HIRING)

Micron

ASIC Design Verification Engineer

Minneapolis, MN · On-site

$142K - $173K/yr

As a technical member of Micron's ASIC Design Verification team, you will have a key role in ... Bachelor's or Master's degree in Electrical Engineering, Computer Engineering or equivalent. * 2+ ...

Micron

Sr. Design Verification Engineer

Minneapolis, MN · On-site

$142K - $173K/yr

Our ASIC Design Verification team develops robust, scalable verification environments for highly ... Bachelor's or Master's degree in Electrical Engineering or Computer Engineering, or equivalent ...

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All JobsGoogle Asic Design Engineer JobsGoogle Asic Design Engineer Jobs in Minnesota

Google Asic Design Engineer information

See Minnesota salary details

$92.1K

$147.1K

$197.8K

How much do google asic design engineer jobs pay per year?

As of Jul 26, 2026, the average yearly pay for google asic design engineer in Minnesota is $147,103.00, according to ZipRecruiter salary data. Most workers in this role earn between $128,800.00 and $176,300.00 per year, depending on experience, location, and employer.

What is the difference between Google Asic Design Engineer vs Google FPGA Design Engineer?

AspectGoogle Asic Design EngineerGoogle FPGA Design Engineer
Required CredentialsBachelor's/Master's in Electrical Engineering or Computer Engineering; experience in ASIC designBachelor's/Master's in Electrical Engineering or Computer Engineering; FPGA design experience
Work EnvironmentDesigning custom silicon chips for Google productsDeveloping and testing FPGA prototypes for hardware acceleration
Employer & Industry UsagePrimarily in semiconductor and hardware design teams at GoogleHardware prototyping and acceleration teams at Google

The main difference between a Google Asic Design Engineer and a Google FPGA Design Engineer lies in their focus: ASIC engineers design custom chips for optimized performance, while FPGA engineers develop flexible hardware prototypes using field-programmable gate arrays. Both roles require strong electrical engineering skills but serve different stages of hardware development.

How does a Google ASIC Design Engineer typically collaborate with cross-functional teams during the chip development process?

As a Google ASIC Design Engineer, you will work closely with teams such as architecture, verification, software, and hardware validation to ensure successful chip delivery. Collaboration often involves regular meetings to align on design specifications, resolve integration issues, and discuss performance optimization. Effective communication is essential, as you’ll need to translate requirements from system architects into detailed hardware designs and provide feedback to verification and validation teams. This cross-functional interaction fosters a dynamic work environment and helps ensure the final product meets Google's rigorous standards.

What does a Google ASIC Design Engineer do?

A Google ASIC Design Engineer is responsible for designing and developing custom integrated circuits, known as Application-Specific Integrated Circuits (ASICs), that power Google's data centers, cloud infrastructure, and consumer devices. Their work involves collaborating with cross-functional teams to define requirements, create architecture, perform logic and physical design, and validate the silicon before production. They use advanced design tools and methodologies to ensure high performance, low power consumption, and reliability. Ultimately, their contributions help improve the efficiency and capabilities of Google's hardware products.

What are the key skills and qualifications needed to thrive as a Google ASIC Design Engineer, and why are they important?

To thrive as a Google ASIC Design Engineer, you need a strong background in electrical engineering, digital logic design, and experience with ASIC development, typically backed by a relevant degree. Familiarity with hardware description languages (such as Verilog or VHDL), EDA tools (like Synopsys or Cadence), and an understanding of SoC architectures are essential, and related certifications can be valuable. Strong problem-solving skills, attention to detail, and effective teamwork and communication abilities help set candidates apart. These skills are crucial for designing reliable, high-performance ASICs that meet Google's specifications and project timelines.
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Google Asic Design Engineer jobs near you
Infographic showing various Google Asic Design Engineer job openings in Minnesota as of July 2026, with employment types broken down into 21% As Needed, 72% Full Time, 4% Part Time, 2% Contract, and 1% Summer. Highlights an 86% Physical, 8% Hybrid, and 6% Remote job distribution, with an average salary of $147,103 per year, or $70.7 per hour.

Staff ASIC Design Engineer

ForwardEdge ASIC LLC

Saint Paul, MN

$140K - $170K/yr

Other

Medical, Retirement, PTO

Posted 5 days ago

Job description

Position Description: At ForwardEdge ASIC we specialize in best-in-class ASIC technology, 100% domestically traceable microelectronic solutions designed for performance in commercial, aerospace, defense, and security sectors. FEASIC operates a full-scale ASIC design shop with cross-disciplinary fluency between digital logic, analog/mixed-signal design, and physical layout, and sits at the intersection of advanced ASIC, FPGA, and microelectronics design. As a wholly owned subsidiary of Lockheed Martin, we combine the agility of a startup with the stability and scale of a Fortune 100 leader. We operate in a nimble, fast-paced environment of 80+ highly experienced and specialized engineers with over 25 years of ASIC/FPGA experience and more than 300 patents. Job SummaryWe are currently seeking a Staff ASIC Design Engineer responsible for developing ASIC and FPGA designs that will be included in an array of complex, innovative and exciting products. Your responsibility will be developing RTL for both ASIC and FPGA design environments. You will collaborate with highly qualified and experienced digital design engineers on the team. You will work closely with verification, analog design, physical design and architecture teams.Key Responsibilities:• Providing leadership to lower-level engineers and working with architects to understand the function and requirements for all types of digital design blocks.• Define, document and design digital/analog interfaces.• Writing detailed implementation plans and specifications for complex design blocks. • Writing Register Transfer Level (RTL) code using industry standard hardware description languages. • Writing lower-level test bench code to verify baseline functionality and features for design blocks.• Writing test plans and coordinating with the Design Verification team to fully verify design blocks.• Synthesizing RTL code using industry standard tools and analyzing results. • Providing RTL updates to meet Power, Performance and Area (PPA) requirements. • Writing and executing plans for the post silicon lab validation. • Providing continued support for design blocks working within a larger system level environment through productization and production. • Process and methodology automation utilizing common scripting languages (i.e. python, perl, tcl). • Provide mentorship and guidance to lower-level digital design engineers. Qualifications:• Bachelor’s or master’s degree in electrical or computer engineering. • Relevant prior experience working at this level as a Staff ASIC Design Engineer. • Experience with RTL coding languages and industry common scripting languages. • Technical leadership experience is a plus. What We Offer• Work-Life Balance: Flexible 9/80 work schedule with every other Friday off• Competitive Comp & Benefits: Healthcare and medical coverage options, 401(k) retirement benefits with company contribution, generous holidays and PTO• Incentives: Eligibility for short-term and long-term incentive programsJoin ForwardEdge ASIC and be part of a team that thrives on innovation and excellence in ASIC design. Together, we build the technology that enables a safer, more resilient world. $140,000.00 - $170,000.00 Annually

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