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Google Asic Design Engineer Jobs in Chaska, MN (NOW HIRING)

Micron

ASIC Design Verification Engineer

Minneapolis, MN · On-site

$142K - $173K/yr

As a technical member of Micron's ASIC Design Verification team, you will have a key role in ... Bachelor's or Master's degree in Electrical Engineering, Computer Engineering or equivalent. * 2+ ...

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All JobsGoogle Asic Design Engineer JobsGoogle Asic Design Engineer Jobs in Chaska, MN

Google Asic Design Engineer information

See Chaska, MN salary details

$100.8K

$161K

$216.6K

How much do google asic design engineer jobs pay per year?

As of Sep 7, 2026, the average yearly pay for google asic design engineer in Chaska, MN is $161,042.00, according to ZipRecruiter salary data. Most workers in this role earn between $141,000.00 and $193,000.00 per year, depending on experience, location, and employer.

What does a Google ASIC Design Engineer do?

A Google ASIC Design Engineer is responsible for designing and developing custom integrated circuits, known as Application-Specific Integrated Circuits (ASICs), that power Google's data centers, cloud infrastructure, and consumer devices. Their work involves collaborating with cross-functional teams to define requirements, create architecture, perform logic and physical design, and validate the silicon before production. They use advanced design tools and methodologies to ensure high performance, low power consumption, and reliability. Ultimately, their contributions help improve the efficiency and capabilities of Google's hardware products.

How does a Google ASIC Design Engineer typically collaborate with cross-functional teams during the chip development process?

As a Google ASIC Design Engineer, you will work closely with teams such as architecture, verification, software, and hardware validation to ensure successful chip delivery. Collaboration often involves regular meetings to align on design specifications, resolve integration issues, and discuss performance optimization. Effective communication is essential, as you’ll need to translate requirements from system architects into detailed hardware designs and provide feedback to verification and validation teams. This cross-functional interaction fosters a dynamic work environment and helps ensure the final product meets Google's rigorous standards.

What are the key skills and qualifications needed to thrive as a Google ASIC Design Engineer, and why are they important?

To thrive as a Google ASIC Design Engineer, you need a strong background in electrical engineering, digital logic design, and experience with ASIC development, typically backed by a relevant degree. Familiarity with hardware description languages (such as Verilog or VHDL), EDA tools (like Synopsys or Cadence), and an understanding of SoC architectures are essential, and related certifications can be valuable. Strong problem-solving skills, attention to detail, and effective teamwork and communication abilities help set candidates apart. These skills are crucial for designing reliable, high-performance ASICs that meet Google's specifications and project timelines.

What is the difference between Google Asic Design Engineer vs Google FPGA Design Engineer?

AspectGoogle Asic Design EngineerGoogle FPGA Design Engineer
Required CredentialsBachelor's/Master's in Electrical Engineering or Computer Engineering; experience in ASIC designBachelor's/Master's in Electrical Engineering or Computer Engineering; FPGA design experience
Work EnvironmentDesigning custom silicon chips for Google productsDeveloping and testing FPGA prototypes for hardware acceleration
Employer & Industry UsagePrimarily in semiconductor and hardware design teams at GoogleHardware prototyping and acceleration teams at Google

The main difference between a Google Asic Design Engineer and a Google FPGA Design Engineer lies in their focus: ASIC engineers design custom chips for optimized performance, while FPGA engineers develop flexible hardware prototypes using field-programmable gate arrays. Both roles require strong electrical engineering skills but serve different stages of hardware development.

Are Google ASIC Design Engineers in demand?

ASIC Design Engineers at Google are in high demand due to the growing need for specialized hardware acceleration and efficient chip designs in data centers and AI applications. Skills in digital design, verification, and hardware description languages like Verilog or VHDL are highly valued, and the role often requires experience with EDA tools and FPGA prototyping. The demand is expected to remain strong as companies continue to develop custom chips for performance and energy efficiency.

How much does a Google ASIC Design Engineer make?

A Google ASIC Design Engineer typically earns a base salary ranging from $120,000 to $200,000 annually, with total compensation often including bonuses and stock options. Compensation varies based on experience, location, and level within the company, and the role requires expertise in hardware design, verification, and EDA tools.

What is the salary of Google ASIC Design Engineer in Google?

The salary for a Google ASIC Design Engineer typically ranges from $120,000 to $200,000 annually, depending on experience, location, and level within the company. Compensation may also include bonuses, stock options, and benefits, reflecting industry standards for specialized hardware design roles at major tech companies.
Google Asic Design Engineer jobs near you
Infographic showing various Google Asic Design Engineer job openings in Chaska, MN as of August 2026, with employment types broken down into 6% As Needed, 72% Full Time, and 22% Contract. Highlights an 94% In-person, and 6% Remote job distribution, with an average salary of $161,042 per year, or $77.4 per hour.

ASIC Physical Design Engineer, Principal

ForwardEdge ASIC LLC

Saint Paul, MN • On-site

$200K - $220K/yr

Other

Medical, Retirement, PTO

Re-posted 11 days ago

Job description

Position Description: At ForwardEdge ASIC we specialize in best-in-class ASIC technology, 100% domestically traceable microelectronic solutions designed for performance in commercial, aerospace, defense, and security sectors. FEASIC operates a full-scale ASIC design shop with cross-disciplinary fluency between digital logic, analog/mixed-signal design, and physical layout, and sits at the intersection of advanced ASIC, FPGA, and microelectronics design. As a wholly owned subsidiary of Lockheed Martin, we combine the agility of a startup with the stability and scale of a Fortune 100 leader. We operate in a nimble, fast-paced environment of 80+ highly experienced and specialized engineers with over 25 years of ASIC/FPGA experience and more than 300 patents. Position SummaryWe are looking for highly experienced ASIC Physical Design / Static Time Analysis (PD/STA) Engineer to work onsite in our St. Paul, MN office to support ASICs, IPs and Chiplet designs. This role is targeted at senior level candidates who can operate with a high degree of RTL2GDS PD implementation and sign-off for tape out.Key Responsibilities • Lead and collaborate with Analog, Verification, Logic and Physical design team members on all design implementation aspects from Synthesis to Tape-Out of various IPs, test chips and SoC/ASIC designs. • Lead with hands-on experience with synthesis, block and chip level implementation with industry standard PnR, STA and EMIR flows and tools• Lead end-to-end timing closure at block/chip levels including MCMM flows and ECO flows • Collaborate with cross functional teams to problem solve solutions across new and changing tools, flows and methodologies• Mentor junior and senior PD engineers through technical reviews, methodology guidance, and hands-on support.• Improve productivity through automation, infrastructure, and methodology enhancements.• Support project planning by identifying risks, tracking progress, and communicating status to technical and program leadership.Qualifications • BS in Electrical, Electronics, Computer Engineering, or 15 years of experience in related field or MS in Electrical, Electronics, Computer Engineering, or 12 years of experience in related field or Ph.D. with 8 years of experience in related field• Experience in advanced technology nodes and understanding of deep sub-micron design problems/solutions and ability to drive design closure in a fast-paced environment• Strong experience in SOC/ASIC design flows, tools and methodologies.• Knowledge of low power design flows such as power gating, multi-Vt, Voltage scaling techniques• Excellent understanding of logic design fundamentals and gate/transistor level implementation• Strong programming skills in Tcl/Perl/Shell/Python• Effective communicator with the ability to influence cross-functional teams.What We Offer• Work-Life Balance: Flexible 9/80 work schedule with every other Friday off• Competitive Comp & Benefits: Healthcare and medical coverage options, 401(k) retirement benefits with company contribution, generous holidays and PTO• Incentives: Eligibility for short-term and long-term incentive programsJoin ForwardEdge ASIC and be part of a team that thrives on innovation and excellence in ASIC design. Together, we build the technology that enables a safer, more resilient world. $200,000.00 - $220,000.00 Annually

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