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Google Asic Design Engineer Jobs in Chaska, MN (NOW HIRING)

Geologics

Advanced ASIC/FPGA Engineer

Bloomington, MN · On-site

$75 - $81/hr

Responsible for definition, design, verification and documentation for ASIC (Application Specific Integrated Circuit) and/or FPGA (Field Programmable Gate Array) developments * Determines ...

Geologics

Advanced ASIC/FPGA Engineer

Bloomington, MN · On-site

$75 - $81/hr

Responsible for definition, design, verification and documentation for ASIC (Application Specific Integrated Circuit) and/or FPGA (Field Programmable Gate Array) developments * Determines ...

Micron

Sr. Design Verification Engineer

Minneapolis, MN

$142K - $173K/yr

Our ASIC Design Verification team develops robust, scalable verification environments for highly ... Bachelor's or Master's degree in Electrical Engineering or Computer Engineering, or equivalent ...

Broadcom

Principal IC Design Engineer

Mendota Heights, MN · On-site

$127K - $203K/yr

The ASIC Product Division in Broadcom is a leading supplier of state-of-the-art SOCs to the world ... We are seeking a motivated and technically strong engineer to join our SOC team to design and ...

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All JobsGoogle Asic Design Engineer JobsGoogle Asic Design Engineer Jobs in Chaska, MN

Google Asic Design Engineer information

See Chaska, MN salary details

$100.8K

$161K

$216.6K

How much do google asic design engineer jobs pay per year?

As of Sep 7, 2026, the average yearly pay for google asic design engineer in Chaska, MN is $161,042.00, according to ZipRecruiter salary data. Most workers in this role earn between $141,000.00 and $193,000.00 per year, depending on experience, location, and employer.

What does a Google ASIC Design Engineer do?

A Google ASIC Design Engineer is responsible for designing and developing custom integrated circuits, known as Application-Specific Integrated Circuits (ASICs), that power Google's data centers, cloud infrastructure, and consumer devices. Their work involves collaborating with cross-functional teams to define requirements, create architecture, perform logic and physical design, and validate the silicon before production. They use advanced design tools and methodologies to ensure high performance, low power consumption, and reliability. Ultimately, their contributions help improve the efficiency and capabilities of Google's hardware products.

How does a Google ASIC Design Engineer typically collaborate with cross-functional teams during the chip development process?

As a Google ASIC Design Engineer, you will work closely with teams such as architecture, verification, software, and hardware validation to ensure successful chip delivery. Collaboration often involves regular meetings to align on design specifications, resolve integration issues, and discuss performance optimization. Effective communication is essential, as you’ll need to translate requirements from system architects into detailed hardware designs and provide feedback to verification and validation teams. This cross-functional interaction fosters a dynamic work environment and helps ensure the final product meets Google's rigorous standards.

What are the key skills and qualifications needed to thrive as a Google ASIC Design Engineer, and why are they important?

To thrive as a Google ASIC Design Engineer, you need a strong background in electrical engineering, digital logic design, and experience with ASIC development, typically backed by a relevant degree. Familiarity with hardware description languages (such as Verilog or VHDL), EDA tools (like Synopsys or Cadence), and an understanding of SoC architectures are essential, and related certifications can be valuable. Strong problem-solving skills, attention to detail, and effective teamwork and communication abilities help set candidates apart. These skills are crucial for designing reliable, high-performance ASICs that meet Google's specifications and project timelines.

What is the difference between Google Asic Design Engineer vs Google FPGA Design Engineer?

AspectGoogle Asic Design EngineerGoogle FPGA Design Engineer
Required CredentialsBachelor's/Master's in Electrical Engineering or Computer Engineering; experience in ASIC designBachelor's/Master's in Electrical Engineering or Computer Engineering; FPGA design experience
Work EnvironmentDesigning custom silicon chips for Google productsDeveloping and testing FPGA prototypes for hardware acceleration
Employer & Industry UsagePrimarily in semiconductor and hardware design teams at GoogleHardware prototyping and acceleration teams at Google

The main difference between a Google Asic Design Engineer and a Google FPGA Design Engineer lies in their focus: ASIC engineers design custom chips for optimized performance, while FPGA engineers develop flexible hardware prototypes using field-programmable gate arrays. Both roles require strong electrical engineering skills but serve different stages of hardware development.

Are Google ASIC Design Engineers in demand?

ASIC Design Engineers at Google are in high demand due to the growing need for specialized hardware acceleration and efficient chip designs in data centers and AI applications. Skills in digital design, verification, and hardware description languages like Verilog or VHDL are highly valued, and the role often requires experience with EDA tools and FPGA prototyping. The demand is expected to remain strong as companies continue to develop custom chips for performance and energy efficiency.

How much does a Google ASIC Design Engineer make?

A Google ASIC Design Engineer typically earns a base salary ranging from $120,000 to $200,000 annually, with total compensation often including bonuses and stock options. Compensation varies based on experience, location, and level within the company, and the role requires expertise in hardware design, verification, and EDA tools.

What is the salary of Google ASIC Design Engineer in Google?

The salary for a Google ASIC Design Engineer typically ranges from $120,000 to $200,000 annually, depending on experience, location, and level within the company. Compensation may also include bonuses, stock options, and benefits, reflecting industry standards for specialized hardware design roles at major tech companies.
Google Asic Design Engineer jobs near you
Infographic showing various Google Asic Design Engineer job openings in Chaska, MN as of August 2026, with employment types broken down into 6% As Needed, 72% Full Time, and 22% Contract. Highlights an 94% In-person, and 6% Remote job distribution, with an average salary of $161,042 per year, or $77.4 per hour.

Advanced ASIC/FPGA Engineer

Geologics

Bloomington, MN • On-site

$75 - $81/hr

Contractor

Re-posted 12 days ago

Job description

GeoLogics is working with a top Aerospace and Defense client looking for a Advanced ASIC/FPGA Engineer in Bloomington, MN

Role: Advanced ASIC/FPGA Engineer

Client: Top Aerospace and Defense company

Clearance: Be able to obtain a clearance, Secret preferred

Location: Bloomington, MN

Education: Bachelor's in STEM 

Rate: $75 to $81 (per hour on a non-benefitted W2 contract)

***No C2C, we can NOT work with outside agencies/vendors, and we can NOT do 1099-US CITIZENSHIP IS REQUIRED***

Job Description:

  • Responsible for definition, design, verification and documentation for ASIC (Application Specific Integrated Circuit) and/or FPGA (Field Programmable Gate Array) developments
  • Determines architecture, system simulation and detailed design approach
  • Defines module interfaces and all aspects of device design and simulation
  • Evaluates the process flow including but not limited to high level design, synthesis, place and route, timing and power utilization
  • Creates test and simulation plans that establish functional criteria
  • Verifies test results and analyzes performance
  • May also review vendor capabilities, foundry technologies, device libraries and simulation tools
  • Participates in the improvement of the ASIC/FPGA organizational processes
  • Supports the generation of technical engineering products by using the appropriate standards, processes, procedures, and tools throughout the ASIC/FPGA development life cycle
  • Contributes to the research and analysis of data, such as customer design proposal specifications, and manuals to determine feasibility of design or application
  • Selects components and equipment based on analysis of specifications and reliability
  • May provide leadership and/or direction to lower level employees
  • Independently determines approach to solutions
  • Contributes to the completion of major programs and projects 
  • Plans and executes project tasks for activities described above

Knowledge, Skills and Abilities:

  • Highly proficient use and understanding of ASIC/FPGA engineering concepts, principles, and theories
  • Highly proficient in the principles and techniques of ASIC/FPGA design
  • Highly proficient understanding of ASIC/FPGA processes
  • Highly proficient knowledge of other related disciplines
  • Keeps abreast of technology trends
  • Highly proficient awareness of business objectives and Engineering's role in achieving • Highly proficient in Microsoft Office applications
  • Highly proficient in ASIC/FPGA design tools
  • Highly proficient written and verbal communications skills
  • Ability to think creatively
  • Ability to multi-task
  • Highly proficient skill in communicating issues, impacts, and corrective actions
  • Highly proficient ability to recognize and clearly report information relevant to sound ASIC/FPGA design
  • Highly proficient ability to develop and sell concepts and ideas
  • Regular contact with senior levels of internal work groups
  • Works under limited direction
  • Contact with project leaders and other professionals within the Engineering department and with project teams across the company
  • Some contact with external customers
  • Identifies opportunities to apply AI for continuous improvement and innovation




Education:DegreeEmployment Type: CONTRACTOR

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