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Google Asic Design Engineer Jobs in Texas (NOW HIRING)

InvestedintheMission

ASIC Design Engineer

Central, TX · On-site

$85 - $120/hr

The ASIC Design Engineer contributes to the design of digital IP blocks for advanced Satellite communication ASICs. This role is an excellent opportunity to grow technical depth in RTL design ...

Cornelis Networks

PCIe ASIC Design Engineer

Austin, TX · On-site

We're seeking engineers who are energized by working on cutting-edge ASIC design and distributed software systems, and who are motivated to push the boundaries on how AI can transform everything from ...

Nvidia

ASIC Design Engineer - Hardware

Austin, TX · Hybrid

Join the NVIDIA System-On-Chip (SOC) group as an ASIC Design Engineer and make a broad impact. You will focus on improving methodologies and delivering system-level IP to measure performance across ...

Apple

Cellular ASIC Design Engineer

Austin, TX

$175K - $308K/yr

Description As a Cellular ASIC Design Engineer, you'll develop and optimize design and implementation methodology for integrated circuits across multiple focus areas including area efficiency, power ...

Apple

Cellular ASIC Design Engineer

Austin, TX

$175K - $308K/yr

Description As a Cellular ASIC Design Engineer, you'll develop and optimize design and implementation methodology for integrated circuits across multiple focus areas including area efficiency, power ...

Apple

Cellular ASIC Design Engineer

Austin, TX

$175K - $308K/yr

Description As a Cellular ASIC Design Engineer, you'll develop and optimize design and implementation methodology for integrated circuits across multiple focus areas including area efficiency, power ...

Amazon

ASIC Engineer, Annapurna Labs

Austin, TX · On-site

$164K/yr

We're looking for an ASIC Design Engineer to help us trail-blaze new technologies and architectures, while ensuring high design quality and making the right trade-offs. Key job responsibilities ...

Amazon

ASIC Engineer, Annapurna Labs

Austin, TX

$164K/yr

We're looking for an ASIC Design Engineer to help us trail-blaze new technologies and architectures, while ensuring high design quality and making the right trade-offs. Key job responsibilities ...

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All JobsGoogle Asic Design Engineer JobsGoogle Asic Design Engineer Jobs in Texas

Google Asic Design Engineer information

See Texas salary details

$87.6K

$139.9K

$188.2K

How much do google asic design engineer jobs pay per year?

As of Aug 9, 2026, the average yearly pay for google asic design engineer in Texas is $139,930.00, according to ZipRecruiter salary data. Most workers in this role earn between $122,500.00 and $167,700.00 per year, depending on experience, location, and employer.

What is the difference between Google Asic Design Engineer vs Google FPGA Design Engineer?

AspectGoogle Asic Design EngineerGoogle FPGA Design Engineer
Required CredentialsBachelor's/Master's in Electrical Engineering or Computer Engineering; experience in ASIC designBachelor's/Master's in Electrical Engineering or Computer Engineering; FPGA design experience
Work EnvironmentDesigning custom silicon chips for Google productsDeveloping and testing FPGA prototypes for hardware acceleration
Employer & Industry UsagePrimarily in semiconductor and hardware design teams at GoogleHardware prototyping and acceleration teams at Google

The main difference between a Google Asic Design Engineer and a Google FPGA Design Engineer lies in their focus: ASIC engineers design custom chips for optimized performance, while FPGA engineers develop flexible hardware prototypes using field-programmable gate arrays. Both roles require strong electrical engineering skills but serve different stages of hardware development.

How does a Google ASIC Design Engineer typically collaborate with cross-functional teams during the chip development process?

As a Google ASIC Design Engineer, you will work closely with teams such as architecture, verification, software, and hardware validation to ensure successful chip delivery. Collaboration often involves regular meetings to align on design specifications, resolve integration issues, and discuss performance optimization. Effective communication is essential, as you’ll need to translate requirements from system architects into detailed hardware designs and provide feedback to verification and validation teams. This cross-functional interaction fosters a dynamic work environment and helps ensure the final product meets Google's rigorous standards.

What does a Google ASIC Design Engineer do?

A Google ASIC Design Engineer is responsible for designing and developing custom integrated circuits, known as Application-Specific Integrated Circuits (ASICs), that power Google's data centers, cloud infrastructure, and consumer devices. Their work involves collaborating with cross-functional teams to define requirements, create architecture, perform logic and physical design, and validate the silicon before production. They use advanced design tools and methodologies to ensure high performance, low power consumption, and reliability. Ultimately, their contributions help improve the efficiency and capabilities of Google's hardware products.

What are the key skills and qualifications needed to thrive as a Google ASIC Design Engineer, and why are they important?

To thrive as a Google ASIC Design Engineer, you need a strong background in electrical engineering, digital logic design, and experience with ASIC development, typically backed by a relevant degree. Familiarity with hardware description languages (such as Verilog or VHDL), EDA tools (like Synopsys or Cadence), and an understanding of SoC architectures are essential, and related certifications can be valuable. Strong problem-solving skills, attention to detail, and effective teamwork and communication abilities help set candidates apart. These skills are crucial for designing reliable, high-performance ASICs that meet Google's specifications and project timelines.
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Google Asic Design Engineer jobs near you
Infographic showing various Google Asic Design Engineer job openings in Texas as of August 2026, with employment types broken down into 6% As Needed, 72% Full Time, and 22% Contract. Highlights an 94% In-person, and 6% Remote job distribution, with an average salary of $139,930 per year, or $67.3 per hour.

ASIC Design Engineer (eInfochips)

Arrow Electronics, Inc.

Sunset Valley, TX • On-site

Full-time

Re-posted yesterday

Job description

Position:ASIC Design Engineer (eInfochips)
Job Description:

Role: Asic Design Engineer

Location: Mountain View CA (Remote)

Note: Seeking candidate with Fusion Compiler and Scripting experince.

What candidate will Be Doing:

  • Proficient in Verilog/System Verilog coding constructs.
  • Knowledge of front-end tools (Verilog simulators, Connectivity tools, CDC checkers, low power static checkers, linting)
  • Experience with high speed PCIe designs and protocols.
  • Experience with Industry standard interface protocols such as AXI, APB, etc.
  • Experience with ARM Fabric IPs.
  • Experience with IPXACT.
  • Understanding of Computer Architecture fundamentals.
  • Ability to write scripts using Python, Tcl, Perl etc.
  • Experience in EDA tools such as VCS, VCLP, Spyglass Lint, Questa CDC, Fusion Compiler, Design Compiler, Genus.
  • Proficiency with UPF (Low power intent)
  • Proficiency in clock crossing techniques.
  • Knowledge of Static Timing Analysis and understanding of timing signoff fundamentals.

What we are looking for:

  • Good in understanding RTL Design and Digital concepts
  • Strong experience with EDA tools: Fusion Compiler, CDC
  • Scripting: Pearl, Python, TCL
  • At-least 5+ years of experience in Verilog Design
  • AMBA AXI bus along-with ARM or C based processor
  • Ensure customer satisfaction.
  • Reporting to customers on daily or weekly progress effectively

Work Arrangement Fully Onsite: Must be able to travel to an Arrow Client office location as requested by Arrow Client leadership.

Location: Mountain View CA (Remote)

About eInfochips:

eInfochips, an Arrow company (Fortune#154), is a leading global provider of product engineering and semiconductor design services. A rich history of over two decades, with over 500+ products developed and 40M deployments in 140 countries, eInfochips continues to fuel technological innovations in multiple verticals. eInfochips has strategic technology partnerships with Qualcomm, NVIDIA, NXP, Analog Devices, Texas Instruments, Amazon, Microsoft and Google to name a few. Along with Arrow’s $38B in revenues, 22,000 employees, and 345 locations serving over 80 countries, eInfochips is primed to accelerate connected products innovation for 150,000+ global clients. eInfochips acts as a catalyst to Arrow’s Sensor-to-Sunset initiative and offers complete edge-to-cloud capabilities for its clients. Please visit www.einfochips.com for our portfolio of product engineering services across

various industries & verticals.

Arrow’s Sensor-to-Sunset initiative and offers complete edge-to-cloud capabilities for its clients. Please visit www.einfochips.com for our portfolio of product engineering services across various industries C verticals.

EEO Statement:

Arrow is an equal opportunity employer. All applicants will be considered for employment without attention to race, color, religion, gender, age, sexual orientation, gender identity, national origin, veteran or disability status.


Location:US-CA-Mountain View, California (Google)
Time Type:Full time
Job Category:Engineering ServicesEEO Statement:

Arrow is an equal opportunity employer. All applicants will be considered for employment without attention to race, color, religion, gender, age, sexual orientation, gender identity, national origin, veteran or disability status. (Arrow EEO/AAP policy)


All Arrow job postings are for existing job vacancies. We anticipate this requisition will be open for a minimum of five days, though it may be open for a longer period of time. We encourage your prompt application.

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