SR. ASIC DESIGN VERIFICATION ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience in building rockets and spacecraft to deploy Starlink, the world's most advanced broadband ...
SR. ASIC DESIGN VERIFICATION ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience in building rockets and spacecraft to deploy Starlink, the world's most advanced broadband ...
ASIC Engineer, Annapurna Labs
Austin, TX · On-site
$164K/yr
We're looking for an ASIC Design Engineer to help us trail-blaze new technologies and architectures, while ensuring high design quality and making the right trade-offs. Key job responsibilities ...
ASIC Engineer, Annapurna Labs
Austin, TX · On-site
$164K/yr
We're looking for an ASIC Design Engineer to help us trail-blaze new technologies and architectures, while ensuring high design quality and making the right trade-offs. Key job responsibilities ...
NVIDIA is seeking an experienced ASIC Floorplan Engineer to design and implement the world's leading SOCs, CPUs, and GPUs. This position offers you a unique opportunity to craft and to influence the ...
NVIDIA is seeking an experienced ASIC Floorplan Engineer to design and implement the world's leading SOCs, CPUs, and GPUs. This position offers you a unique opportunity to craft and to influence the ...
Your Team, Your Impact We are seeking a highly motivated and technically strong ASIC CAD Flow & Infrastructure Engineer to drive the development, deployment, and support of next-generation ASIC ...
Your Team, Your Impact We are seeking a highly motivated and technically strong ASIC CAD Flow & Infrastructure Engineer to drive the development, deployment, and support of next-generation ASIC ...
Your Team, Your Impact We are seeking a highly motivated and technically strong ASIC CAD Flow & Infrastructure Engineer to drive the development, deployment, and support of next-generation ASIC ...
Your Team, Your Impact We are seeking a highly motivated and technically strong ASIC CAD Flow & Infrastructure Engineer to drive the development, deployment, and support of next-generation ASIC ...
ASIC Implementation Engineer - Static Verification Responsibilities: * Perform Flat and ... Work closely with the Design Engineers, DV Engineers, Emulation Engineers in supporting them with ...
ASIC Implementation Engineer - Static Verification Responsibilities: * Perform Flat and ... Work closely with the Design Engineers, DV Engineers, Emulation Engineers in supporting them with ...
We're seeking engineers who are energized by working on cutting-edge ASIC design and distributed software systems, and who are motivated to push the boundaries on how AI can transform everything from ...
We're seeking engineers who are energized by working on cutting-edge ASIC design and distributed software systems, and who are motivated to push the boundaries on how AI can transform everything from ...
In this role, you will collaborate with architecture, design, and verification teams to deliver ... ASIC Engineer, Implementation - Timing Responsibilities: * Develop Timing Constraints for RTL ...
In this role, you will collaborate with architecture, design, and verification teams to deliver ... ASIC Engineer, Implementation - Timing Responsibilities: * Develop Timing Constraints for RTL ...
In order to achieve this, Apple's best-in-class chip is driven by top notch design engineers who implement various blocks of the chip and deliver high quality components to SoC. This is a high ...
In order to achieve this, Apple's best-in-class chip is driven by top notch design engineers who implement various blocks of the chip and deliver high quality components to SoC. This is a high ...
We are now looking for an ASIC Design Efficiency Engineer! NVIDIA is seeking extraordinary methodology engineers to design hardware accelerators and processors on our next-generation mobile, embedded ...
We are now looking for an ASIC Design Efficiency Engineer! NVIDIA is seeking extraordinary methodology engineers to design hardware accelerators and processors on our next-generation mobile, embedded ...
ASIC Design Engineer - Fabric/Interconnect
$184K - $324K/yr
In order to achieve this, Apple's best-in-class chip is driven by top notch design engineers who implement various blocks of the chip and deliver high quality components to SoC. This is a high ...
ASIC Design Engineer - Fabric/Interconnect
$184K - $324K/yr
In order to achieve this, Apple's best-in-class chip is driven by top notch design engineers who implement various blocks of the chip and deliver high quality components to SoC. This is a high ...
ASIC Design Engineer - Fabric/Interconnect
$184K - $324K/yr
In order to achieve this, Apple's best-in-class chip is driven by top notch design engineers who implement various blocks of the chip and deliver high quality components to SoC. This is a high ...
ASIC Design Engineer - Fabric/Interconnect
$184K - $324K/yr
In order to achieve this, Apple's best-in-class chip is driven by top notch design engineers who implement various blocks of the chip and deliver high quality components to SoC. This is a high ...
ASIC Design Engineer - Fabric/Interconnect
$150K - $277K/yr
In order to achieve this, Apple's best-in-class chip is driven by top notch design engineers who implement various blocks of the chip and deliver high quality components to SoC. This is a high ...
ASIC Design Engineer - Fabric/Interconnect
$150K - $277K/yr
In order to achieve this, Apple's best-in-class chip is driven by top notch design engineers who implement various blocks of the chip and deliver high quality components to SoC. This is a high ...
In order to achieve this, Apple's best-in-class chip is driven by top notch design engineers who implement various blocks of the chip and deliver high quality components to SoC. This is a high ...
In order to achieve this, Apple's best-in-class chip is driven by top notch design engineers who implement various blocks of the chip and deliver high quality components to SoC. This is a high ...
ASIC Design Engineer - Fabric/Interconnect
$150K - $277K/yr
In order to achieve this, Apple's best-in-class chip is driven by top notch design engineers who implement various blocks of the chip and deliver high quality components to SoC. This is a high ...
ASIC Design Engineer - Fabric/Interconnect
$150K - $277K/yr
In order to achieve this, Apple's best-in-class chip is driven by top notch design engineers who implement various blocks of the chip and deliver high quality components to SoC. This is a high ...
Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars. SR. ASIC DESIGN VERIFICATION ENGINEER (SILICON ENGINEERING) At ...
Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars. SR. ASIC DESIGN VERIFICATION ENGINEER (SILICON ENGINEERING) At ...
Senior ASIC Physical Design Engineer
Austin, TX · On-site
$165K - $241K/yr
Your Impact As a Physical Design Engineer, you will play a key role in the full RTL-to-GDSII ... Bachelor's degree in Electrical or Computer engineering and 7+ years of ASIC relevant experience ...
Senior ASIC Physical Design Engineer
Austin, TX · On-site
$165K - $241K/yr
Your Impact As a Physical Design Engineer, you will play a key role in the full RTL-to-GDSII ... Bachelor's degree in Electrical or Computer engineering and 7+ years of ASIC relevant experience ...
Physical Design Engineer, Sr. Staff
Austin, TX · On-site
$164 - $246/hr
As a Qualcomm ASIC Engineer, you will define, model, design (digital and/or analog), optimize, verify, validate, implement, and document IP (block/SoC) development for a variety of high performance ...
Physical Design Engineer, Sr. Staff
Austin, TX · On-site
$164 - $246/hr
As a Qualcomm ASIC Engineer, you will define, model, design (digital and/or analog), optimize, verify, validate, implement, and document IP (block/SoC) development for a variety of high performance ...
ASIC Design Verification Technical Leader - Acacia (hybrid)
Austin, TX · Hybrid
$174K - $253K/yr
Your Impact The ASIC Design Verification Technical Lead Engineer will be working on next-generation 100G-1.6T coherent optical communications products. This role is for a senior contributor ...
ASIC Design Verification Technical Leader - Acacia (hybrid)
Austin, TX · Hybrid
$174K - $253K/yr
Your Impact The ASIC Design Verification Technical Lead Engineer will be working on next-generation 100G-1.6T coherent optical communications products. This role is for a senior contributor ...
As an ASIC Engineer specializing in architecture, performance and modeling, you will define and ... Collaborate with architecture, RTL design, and physical design teams to translate performance ...
As an ASIC Engineer specializing in architecture, performance and modeling, you will define and ... Collaborate with architecture, RTL design, and physical design teams to translate performance ...
Google Asic Design Engineer information
See Texas salary details
$87.6K - $96.7K
16% of jobs
$96.7K - $105.9K
3% of jobs
$105.9K - $115K
4% of jobs
$117.7K is the 25th percentile. Wages below this are outliers.
$115K - $124.2K
6% of jobs
The median wage is $129.9K / yr.
$124.2K - $133.3K
33% of jobs
$133.3K - $142.5K
3% of jobs
$142.5K - $151.6K
2% of jobs
$157.6K is the 75th percentile. Wages above this are outliers.
$151.6K - $160.8K
12% of jobs
$160.8K - $169.9K
5% of jobs
$169.9K - $179K
4% of jobs
$179K - $188.2K
12% of jobs
$87.6K
$139.9K
$188.2K
How much do google asic design engineer jobs pay per year?
As of Aug 10, 2026, the average yearly pay for google asic design engineer in Texas is $139,930.00, according to ZipRecruiter salary data. Most workers in this role earn between $122,500.00 and $167,700.00 per year, depending on experience, location, and employer.
What is the difference between Google Asic Design Engineer vs Google FPGA Design Engineer?
| Aspect | Google Asic Design Engineer | Google FPGA Design Engineer |
|---|---|---|
| Required Credentials | Bachelor's/Master's in Electrical Engineering or Computer Engineering; experience in ASIC design | Bachelor's/Master's in Electrical Engineering or Computer Engineering; FPGA design experience |
| Work Environment | Designing custom silicon chips for Google products | Developing and testing FPGA prototypes for hardware acceleration |
| Employer & Industry Usage | Primarily in semiconductor and hardware design teams at Google | Hardware prototyping and acceleration teams at Google |
The main difference between a Google Asic Design Engineer and a Google FPGA Design Engineer lies in their focus: ASIC engineers design custom chips for optimized performance, while FPGA engineers develop flexible hardware prototypes using field-programmable gate arrays. Both roles require strong electrical engineering skills but serve different stages of hardware development.
How does a Google ASIC Design Engineer typically collaborate with cross-functional teams during the chip development process?
As a Google ASIC Design Engineer, you will work closely with teams such as architecture, verification, software, and hardware validation to ensure successful chip delivery. Collaboration often involves regular meetings to align on design specifications, resolve integration issues, and discuss performance optimization. Effective communication is essential, as you’ll need to translate requirements from system architects into detailed hardware designs and provide feedback to verification and validation teams. This cross-functional interaction fosters a dynamic work environment and helps ensure the final product meets Google's rigorous standards.
What does a Google ASIC Design Engineer do?
A Google ASIC Design Engineer is responsible for designing and developing custom integrated circuits, known as Application-Specific Integrated Circuits (ASICs), that power Google's data centers, cloud infrastructure, and consumer devices. Their work involves collaborating with cross-functional teams to define requirements, create architecture, perform logic and physical design, and validate the silicon before production. They use advanced design tools and methodologies to ensure high performance, low power consumption, and reliability. Ultimately, their contributions help improve the efficiency and capabilities of Google's hardware products.
What are the key skills and qualifications needed to thrive as a Google ASIC Design Engineer, and why are they important?
To thrive as a Google ASIC Design Engineer, you need a strong background in electrical engineering, digital logic design, and experience with ASIC development, typically backed by a relevant degree. Familiarity with hardware description languages (such as Verilog or VHDL), EDA tools (like Synopsys or Cadence), and an understanding of SoC architectures are essential, and related certifications can be valuable. Strong problem-solving skills, attention to detail, and effective teamwork and communication abilities help set candidates apart. These skills are crucial for designing reliable, high-performance ASICs that meet Google's specifications and project timelines.
What are popular job titles related to Google Asic Design Engineer jobs in Texas? For Google Asic Design Engineer jobs in Texas, the most frequently searched job titles are:
What job categories do people searching Google Asic Design Engineer jobs in Texas look for? The top searched job categories for Google Asic Design Engineer jobs in Texas are:
What cities in Texas are hiring for Google Asic Design Engineer jobs? Cities in Texas with the most Google Asic Design Engineer job openings:
Full-time
Re-posted 20 days ago
SpaceX rating
8.8
Based on 147 frontline employees who took The Breakroom Quiz
15th of 72 rated aerospace companies
Job description
SR. ASIC DESIGN VERIFICATION ENGINEER (SILICON ENGINEERING)
At SpaceX we're leveraging our experience in building rockets and spacecraft to deploy Starlink, the world's most advanced broadband internet system. Starlink is the world's largest satellite constellation and is providing fast, reliable internet to millions of users worldwide. We design, build, test, and operate all parts of the system - thousands of satellites, consumer receivers that allow users to connect within minutes of unboxing, and the software that brings it all together. We've only begun to scratch the surface of Starlink's potential global impact are looking for best-in-class engineers to help maximize Starlink's utility for communities and businesses around the globe.
We are seeking a motivated, proactive, and intellectually curious engineer who will work alongside world-class cross-disciplinary teams (systems, firmware, architecture, design, validation, product engineering, ASIC implementation). In this role, you will be developing cutting-edge next-generation ASICs for deployment in space and ground infrastructures around the globe. These chips are enabling connectivity in places it has previously not been available, affordable or reliable. Your efforts will help deliver cutting-edge solutions that will expand the performance and capabilities of the Starlink network.
RESPONSIBILITIES:
- Responsible for digital ASIC verification at block and system level
- Write and review test plans, develop test harnesses and test sequences
- Responsible for test plan execution, running regressions, code and functional coverage closure
- Contribute towards pre-silicon verification, chip bring-up and post-silicon validation
- Be a hands-on self-starter who can execute the steps required to fully verify a complex digital designs
BASIC QUALIFICATIONS:
- Bachelor's degree in electrical engineering or computer engineering
- 5+ years of experience with design verification and test bench development
PREFERRED SKILLS AND EXPERIENCE:
- Advanced degree in electrical engineering or computer engineering
- Experience with verification methodologies such as UVM/OVM/VMM
- Strong object-oriented programming knowledge
- Strong problem-solving and coding skills
- Experience in constrained random verification
- Expertise in developing test plans, implementing coverage models, and analyzing results
- Experience with scripting languages, e.g. Python for automation
- RTL design, chip bring-up, and post-silicon validation experience
- Ability to work in a dynamic environment with changing needs and requirements
ADDITIONAL REQUIREMENTS:
- Ability to work extended hours and weekends as needed to meet critical milestones
About SpaceX
Sourced by ZipRecruiter
Industry
Aerospace product and parts manufacturing, data services, guided missile and space vehicle manufacturing and satellite telecommunications
Company size
1,001 - 5,000 Employees
Headquarters location
Hawthorne, CA, US