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Google Asic Design Engineer Jobs (NOW HIRING)

Credo, Inc

Principal ASIC Design Engineer

San Jose, CA · On-site

$180K - $210K/yr

About the Role As a Principal ASIC Design Engineer, you will be responsible for all aspects of front-end ASIC design, including RTL implementation and verification of complex logic blocks. You will ...

Atom Computing

Principal ASIC Design Engineer

Boulder, CO

$180K - $220K/yr

... engineering, specifically in ASIC/SoC environments. Qualifications * Have gone through 2 or more complete ASIC design cycles. * Experience porting designs from FPGA prototypes to ASICs * Proficiency ...

Atom Computing

Principal ASIC Design Engineer

Austin, TX

$180K - $220K/yr

... engineering, specifically in ASIC/SoC environments. Qualifications * Have gone through 2 or more complete ASIC design cycles. * Experience porting designs from FPGA prototypes to ASICs * Proficiency ...

Nvidia

Senior ASIC Design Engineer

Santa Clara, CA · Hybrid

NVIDIA is seeking ASIC Design Engineers to implement the world's leading SoC's and GPU's. This position offers the opportunity to have real impact in a multifaceted, technology-focused company ...

Atom Computing

Principal ASIC Design Engineer

Austin, TX

$180K - $220K/yr

... engineering, specifically in ASIC/SoC environments. Qualifications * Have gone through 2 or more complete ASIC design cycles. * Experience porting designs from FPGA prototypes to ASICs * Proficiency ...

Fermilab

Jr. ASIC Design Engineer

Batavia, NY · Hybrid

$70K - $93K/yr

We are looking for a Junior ASIC Design Engineer to lead and contribute to research activities and engineering work focused on developing custom instrumentation for extreme radiation and/or cryogenic ...

Infoyogi LLC

ASIC/RTL Design Engineer

San Jose, CA

ASIC/RTL Design Engineer Location: San Jose, CA Duration : 12 months plus JOB DUTIES: The work will expose the designer to a number of IP including ARM cores, Ethernet, DDR, DMA, PCIE, SATA ...

Fermilab

Jr. ASIC Design Engineer

Batavia, IL · On-site

$70K - $93K/yr

We are looking for a Junior ASIC Design Engineer to lead and contribute to research activities and engineering work focused on developing custom instrumentation for extreme radiation and/or cryogenic ...

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All JobsGoogle Asic Design Engineer Jobs

Google Asic Design Engineer information

See salary details

$94K

$150.2K

$202K

How much do google asic design engineer jobs pay per year?

As of Jun 16, 2026, the average yearly pay for google asic design engineer in the United States is $150,195.00, according to ZipRecruiter salary data. Most workers in this role earn between $131,500.00 and $180,000.00 per year, depending on experience, location, and employer.

What is the difference between Google Asic Design Engineer vs Google FPGA Design Engineer?

AspectGoogle Asic Design EngineerGoogle FPGA Design Engineer
Required CredentialsBachelor's/Master's in Electrical Engineering or Computer Engineering; experience in ASIC designBachelor's/Master's in Electrical Engineering or Computer Engineering; FPGA design experience
Work EnvironmentDesigning custom silicon chips for Google productsDeveloping and testing FPGA prototypes for hardware acceleration
Employer & Industry UsagePrimarily in semiconductor and hardware design teams at GoogleHardware prototyping and acceleration teams at Google

The main difference between a Google Asic Design Engineer and a Google FPGA Design Engineer lies in their focus: ASIC engineers design custom chips for optimized performance, while FPGA engineers develop flexible hardware prototypes using field-programmable gate arrays. Both roles require strong electrical engineering skills but serve different stages of hardware development.

How does a Google ASIC Design Engineer typically collaborate with cross-functional teams during the chip development process?

As a Google ASIC Design Engineer, you will work closely with teams such as architecture, verification, software, and hardware validation to ensure successful chip delivery. Collaboration often involves regular meetings to align on design specifications, resolve integration issues, and discuss performance optimization. Effective communication is essential, as you’ll need to translate requirements from system architects into detailed hardware designs and provide feedback to verification and validation teams. This cross-functional interaction fosters a dynamic work environment and helps ensure the final product meets Google's rigorous standards.

What does a Google ASIC Design Engineer do?

A Google ASIC Design Engineer is responsible for designing and developing custom integrated circuits, known as Application-Specific Integrated Circuits (ASICs), that power Google's data centers, cloud infrastructure, and consumer devices. Their work involves collaborating with cross-functional teams to define requirements, create architecture, perform logic and physical design, and validate the silicon before production. They use advanced design tools and methodologies to ensure high performance, low power consumption, and reliability. Ultimately, their contributions help improve the efficiency and capabilities of Google's hardware products.

What are the key skills and qualifications needed to thrive as a Google ASIC Design Engineer, and why are they important?

To thrive as a Google ASIC Design Engineer, you need a strong background in electrical engineering, digital logic design, and experience with ASIC development, typically backed by a relevant degree. Familiarity with hardware description languages (such as Verilog or VHDL), EDA tools (like Synopsys or Cadence), and an understanding of SoC architectures are essential, and related certifications can be valuable. Strong problem-solving skills, attention to detail, and effective teamwork and communication abilities help set candidates apart. These skills are crucial for designing reliable, high-performance ASICs that meet Google's specifications and project timelines.
More about Google Asic Design Engineer jobs
What cities are hiring for Google Asic Design Engineer jobs? Cities with the most Google Asic Design Engineer job openings:
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What job categories do people searching Google Asic Design Engineer jobs look for? The top searched job categories for Google Asic Design Engineer jobs are:
Google Asic Design Engineer jobs near you
Infographic showing various Google Asic Design Engineer job openings in the United States as of June 2026, with employment types broken down into 84% Full Time, 8% Part Time, and 8% Contract. Highlights an 41% In-person, 17% Hybrid, and 42% Remote job distribution, with an average salary of $150,195 per year, or $72.2 per hour.
Senior ASIC Design Engineer

Senior ASIC Design Engineer

Nvidia Corporation

Santa Clara, CA • On-site

Full-time

Posted 24 days ago

Job description

We are now looking for a Senior ASIC Design Engineer.
NVIDIA is seeking ASIC Design Engineers to implement the world's leading SoC's and GPU's. This position offers the opportunity to have real impact in a multifaceted, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. We have crafted a team of outstanding people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform for the future of computing!
What you'll be doing:
  • As a key member of the GPU Design team, you will implement, document and deliver high performance, area and power efficient RTL to achieve design targets and specifications.
  • Analyze architectural trade-offs based on features, performance requirements and system limitations.
  • Craft micro-architecture, implement in RTL, and deliver a fully verified, synthesis/timing clean design.
  • Collaborate and coordinate with architects, other designers, pre- and post-silicon verification teams, synthesis, timing and back-end teams to accomplish your tasks.
  • Work on a broad list of IPs such as GPU's work scheduler, time distribution system, interrupt controllers, and DMA engines.
  • Architect features to help silicon debug and support post-silicon validation activities.

What we need to see:
  • Bachelors Degree or equivalent experience in Electrical Engineering, Computer Engineering or Computer Science.
  • 8+ years of meaningful work experience.
  • Experience in micro-architecture and RTL development (Verilog), focused on arbiters, scheduling, synchronization & bus protocols, interconnect networks and/or caches.
  • Great understanding of ASIC design flow including RTL design, verification, logic synthesis and timing analysis.
  • Exposure to Digital systems and VLSI design, Computer Architecture, and Computer Arithmetic is required.
  • Strong interpersonal skills and an excellent teammate.

Ways to stand out from the crowd:
  • Strong C/C++, Python or Perl skills.
  • Good debugging and analytical skills.

NVIDIA is widely considered to be one of the technology world's most desirable employers. We have some of the most forward-thinking and hardworking people in the world working for us. If you are creative, autonomous and love a challenge, we want to hear from you.
#LI-Hybrid
Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 168,000 USD - 264,500 USD for Level 4, and 196,000 USD - 310,500 USD for Level 5.
You will also be eligible for equity and benefits.
Applications for this job will be accepted at least until March 14, 2026.
This posting is for an existing vacancy.
NVIDIA uses AI tools in its recruiting processes.
NVIDIA is committed to fostering a diverse work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.
Nvidia logo

About Nvidia

Sourced by ZipRecruiter

NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It's a unique legacy of innovation that's fueled by great technology--and amazing people. Today, we're tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing what's never been done before takes vision, innovation, and the world's best talent.

Industry

Computer and electronic product manufacturing

Company size

10,000+ Employees

Headquarters location

Santa Clara, CA, US

Year founded

1993

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