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Google Asic Design Engineer Jobs in Utah (NOW HIRING)

Raytheon

Senior FPGA Design Engineer

Provo, UT

$116K - $160K/yr

As a Senior FPGA Design Engineer you will develop FPGA designs for all major vendors and device ... FPGA/ASIC design, including VHDL and/or Verilog coding or FPGA/ASIC verification using ...

Atonom

AI Workflow & Design Engineer

Provo, UT · On-site

Salary: $60,000 to $90,000 AI Workflow & Design Engineer, Marketing | Full-Time | On-Site (Provo ... Google Suite Why Join * Direct development: You will work closely with the Marketing leadership ...

Atonom

AI Workflow & Design Engineer

Provo, UT · On-site

$60K - $90K/yr

AI Workflow & Design Engineer, Marketing | Full-Time | On-Site (Provo, UT) About Atonom At Atonom ... Google Suite Why Join * Direct development: You will work closely with the Marketing leadership ...

Atonom

AI Workflow & Design Engineer

Provo, UT

AI Workflow & Design Engineer, Marketing | Full-Time | On-Site (Provo, UT) About Atonom At Atonom ... Google Suite Why Join * Direct development: You will work closely with the Marketing leadership ...

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All JobsGoogle Asic Design Engineer JobsGoogle Asic Design Engineer Jobs in Utah

Google Asic Design Engineer information

See Utah salary details

$85.6K

$136.7K

$183.9K

How much do google asic design engineer jobs pay per year?

As of Jul 15, 2026, the average yearly pay for google asic design engineer in Utah is $136,734.00, according to ZipRecruiter salary data. Most workers in this role earn between $119,700.00 and $163,900.00 per year, depending on experience, location, and employer.

What is the difference between Google Asic Design Engineer vs Google FPGA Design Engineer?

AspectGoogle Asic Design EngineerGoogle FPGA Design Engineer
Required CredentialsBachelor's/Master's in Electrical Engineering or Computer Engineering; experience in ASIC designBachelor's/Master's in Electrical Engineering or Computer Engineering; FPGA design experience
Work EnvironmentDesigning custom silicon chips for Google productsDeveloping and testing FPGA prototypes for hardware acceleration
Employer & Industry UsagePrimarily in semiconductor and hardware design teams at GoogleHardware prototyping and acceleration teams at Google

The main difference between a Google Asic Design Engineer and a Google FPGA Design Engineer lies in their focus: ASIC engineers design custom chips for optimized performance, while FPGA engineers develop flexible hardware prototypes using field-programmable gate arrays. Both roles require strong electrical engineering skills but serve different stages of hardware development.

How does a Google ASIC Design Engineer typically collaborate with cross-functional teams during the chip development process?

As a Google ASIC Design Engineer, you will work closely with teams such as architecture, verification, software, and hardware validation to ensure successful chip delivery. Collaboration often involves regular meetings to align on design specifications, resolve integration issues, and discuss performance optimization. Effective communication is essential, as you’ll need to translate requirements from system architects into detailed hardware designs and provide feedback to verification and validation teams. This cross-functional interaction fosters a dynamic work environment and helps ensure the final product meets Google's rigorous standards.

What does a Google ASIC Design Engineer do?

A Google ASIC Design Engineer is responsible for designing and developing custom integrated circuits, known as Application-Specific Integrated Circuits (ASICs), that power Google's data centers, cloud infrastructure, and consumer devices. Their work involves collaborating with cross-functional teams to define requirements, create architecture, perform logic and physical design, and validate the silicon before production. They use advanced design tools and methodologies to ensure high performance, low power consumption, and reliability. Ultimately, their contributions help improve the efficiency and capabilities of Google's hardware products.

What are the key skills and qualifications needed to thrive as a Google ASIC Design Engineer, and why are they important?

To thrive as a Google ASIC Design Engineer, you need a strong background in electrical engineering, digital logic design, and experience with ASIC development, typically backed by a relevant degree. Familiarity with hardware description languages (such as Verilog or VHDL), EDA tools (like Synopsys or Cadence), and an understanding of SoC architectures are essential, and related certifications can be valuable. Strong problem-solving skills, attention to detail, and effective teamwork and communication abilities help set candidates apart. These skills are crucial for designing reliable, high-performance ASICs that meet Google's specifications and project timelines.
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Google Asic Design Engineer jobs near you
Infographic showing various Google Asic Design Engineer job openings in Utah as of July 2026, with employment types broken down into 91% Full Time, 5% Part Time, 2% Contract, and 2% Summer. Highlights an 89% Physical, 6% Hybrid, and 5% Remote job distribution, with an average salary of $136,734 per year, or $65.7 per hour.

Direct-Hire -- Principal Digital ASIC Design Engineer -- Clearfield, UT (Onsite)

TWC Global Services LLC

Clearfield, UT • On-site

$126K/yr

Full-time

Re-posted 20 days ago

Job description

Job Title: Principal Digital ASIC Design Engineer

Location: Clearfield, UT (Onsite)

Job Type: Direct-Hire Position

Industry(ies) - Aerospace / Defense

Primary Skills - Digital ASIC design

Secondary Skills - Digital IC design

Occupational Categories - Engineering/ Manufacturing/ Production/ Operations

Job Description:

We are seeking talented and motivated individuals to tackle challenging engineering problems in advanced digital IC design. 

  • As a Principal Digital ASIC Designer, you will be responsible for designing high-performance digital ASICs in advanced technologies.
  • You will be responsible for implementing designs from RTL through synthesis.
  • You will work in multi-disciplinary teams with opportunities to learn, grow and contribute to a variety of projects in different application areas.

Duties/Responsibilities:

  • Drive solutions to complex problems with limited direction contribute to requirements development, propose ways forward, and adapt appropriately to changes in requirements.
  • Independently performs complex ASIC architectures and designs.
  • Provide insight and suggest design modifications based on simulation results.
  • Identify program/system-level technical risks and develop and execute mitigation strategies.
  • Manage a task with multiple engineers and effectively communicate status to project leadership and customers.
  • Mentor less experienced engineers and provide thoughtful, constructive feedback.
  • Perform other duties as assigned.

Skills/Abilities:

  • Proficiency in ASIC design, microprocessor programming or embedded computing.
  • Understanding of ASIC design and general computer architecture.
  • Ability to write detailed design specifications.
  • Computer programming and coding abilities.
  • Excellent verbal and written communication skills.
  • Excellent mathematical skills.
  • Excellent organizational skills and attention to detail.
  • Excellent time management skills with the proven ability to meet deadlines.
  • Strong analytical and problem-solving skills.
  • Ability to prioritize tasks.
  • Thorough understanding of engineering theories and procedures.

Education:

  • Requires bachelor's degree in engineering, or related field. Master’s degree preferred.

Experience:

  • Requires 7-10 years of experience with a bachelor's degree.

Additional Job Description:

  • Applicants should possess solid skills in front-end digital systems design with experience in design flows from Cadence or Synopsys.
  • Be fluent in System Verilog, Verilog or VHDL and familiar with LINT, simulation and synthesis.
  • Familiarity with architectures for secure systems design, e.g., cryptographic encoders / decoders or tagged processor architectures is a plus.
  • Demonstrated experience with successful tape-outs at advanced nodes is desired. Experience leading and managing design teams is also a plus.
  • Applicants selected for this position will be required to obtain and maintain a U.S. Security Clearance.