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Google Asic Design Engineer Jobs in Utah (NOW HIRING)

Google AI Lead Architect

Salt Lake City, UT · On-site

$53.50 - $73.25/hr

Google AI Lead Architect/AI & Engineering: Join our AI & Engineering team in transforming ... Engineering as a Service provides complete design, implementation, and technology operations ...

Platform Engineer (DevOps)

Salt Lake City, UT · On-site

$52 - $71.25/hr

Design, deploy, and support scalable cloud infrastructure on Google Cloud Platform (preferred) or AWS using cloud engineering best practices * Troubleshoot complex platform, infrastructure ...

Platform Engineer (DevOps)

Salt Lake City, UT · On-site

$52 - $71.25/hr

Design, deploy, and support scalable cloud infrastructure on Google Cloud Platform (preferred) or AWS using cloud engineering best practices * Troubleshoot complex platform, infrastructure ...

Platform Engineer (DevOps)

Salt Lake City, UT · On-site

$52 - $71.25/hr

Design, deploy, and support scalable cloud infrastructure on Google Cloud Platform (preferred) or AWS using cloud engineering best practices * Troubleshoot complex platform, infrastructure ...

Platform Engineer (DevOps)

Salt Lake City, UT · On-site

$51 - $70/hr

... Design, deploy, and support scalable cloud infrastructure on Google Cloud Platform (preferred) or AWS using cloud engineering best practices • Troubleshoot complex platform, infrastructure ...

Platform Engineer (DevOps)

Salt Lake City, UT · On-site

$51 - $70/hr

... Design, deploy, and support scalable cloud infrastructure on Google Cloud Platform (preferred) or AWS using cloud engineering best practices • Troubleshoot complex platform, infrastructure ...

Showing results 21-40

Google Asic Design Engineer information

See Utah salary details

$85.6K

$136.7K

$183.9K

How much do google asic design engineer jobs pay per year?

As of Aug 21, 2026, the average yearly pay for google asic design engineer in Utah is $136,734.00, according to ZipRecruiter salary data. Most workers in this role earn between $119,700.00 and $163,900.00 per year, depending on experience, location, and employer.

What does a Google ASIC Design Engineer do?

A Google ASIC Design Engineer is responsible for designing and developing custom integrated circuits, known as Application-Specific Integrated Circuits (ASICs), that power Google's data centers, cloud infrastructure, and consumer devices. Their work involves collaborating with cross-functional teams to define requirements, create architecture, perform logic and physical design, and validate the silicon before production. They use advanced design tools and methodologies to ensure high performance, low power consumption, and reliability. Ultimately, their contributions help improve the efficiency and capabilities of Google's hardware products.

How does a Google ASIC Design Engineer typically collaborate with cross-functional teams during the chip development process?

As a Google ASIC Design Engineer, you will work closely with teams such as architecture, verification, software, and hardware validation to ensure successful chip delivery. Collaboration often involves regular meetings to align on design specifications, resolve integration issues, and discuss performance optimization. Effective communication is essential, as you’ll need to translate requirements from system architects into detailed hardware designs and provide feedback to verification and validation teams. This cross-functional interaction fosters a dynamic work environment and helps ensure the final product meets Google's rigorous standards.

What are the key skills and qualifications needed to thrive as a Google ASIC Design Engineer, and why are they important?

To thrive as a Google ASIC Design Engineer, you need a strong background in electrical engineering, digital logic design, and experience with ASIC development, typically backed by a relevant degree. Familiarity with hardware description languages (such as Verilog or VHDL), EDA tools (like Synopsys or Cadence), and an understanding of SoC architectures are essential, and related certifications can be valuable. Strong problem-solving skills, attention to detail, and effective teamwork and communication abilities help set candidates apart. These skills are crucial for designing reliable, high-performance ASICs that meet Google's specifications and project timelines.

What is the difference between Google Asic Design Engineer vs Google FPGA Design Engineer?

AspectGoogle Asic Design EngineerGoogle FPGA Design Engineer
Required CredentialsBachelor's/Master's in Electrical Engineering or Computer Engineering; experience in ASIC designBachelor's/Master's in Electrical Engineering or Computer Engineering; FPGA design experience
Work EnvironmentDesigning custom silicon chips for Google productsDeveloping and testing FPGA prototypes for hardware acceleration
Employer & Industry UsagePrimarily in semiconductor and hardware design teams at GoogleHardware prototyping and acceleration teams at Google

The main difference between a Google Asic Design Engineer and a Google FPGA Design Engineer lies in their focus: ASIC engineers design custom chips for optimized performance, while FPGA engineers develop flexible hardware prototypes using field-programmable gate arrays. Both roles require strong electrical engineering skills but serve different stages of hardware development.

Are Google ASIC Design Engineers in demand?

ASIC Design Engineers at Google are in high demand due to the growing need for specialized hardware acceleration and efficient chip designs in data centers and AI applications. Skills in digital design, verification, and hardware description languages like Verilog or VHDL are highly valued, and the role often requires experience with EDA tools and FPGA prototyping. The demand is expected to remain strong as companies continue to develop custom chips for performance and energy efficiency.

How much does a Google ASIC Design Engineer make?

A Google ASIC Design Engineer typically earns a base salary ranging from $120,000 to $200,000 annually, with total compensation often including bonuses and stock options. Compensation varies based on experience, location, and level within the company, and the role requires expertise in hardware design, verification, and EDA tools.

What is the salary of Google ASIC Design Engineer in Google?

The salary for a Google ASIC Design Engineer typically ranges from $120,000 to $200,000 annually, depending on experience, location, and level within the company. Compensation may also include bonuses, stock options, and benefits, reflecting industry standards for specialized hardware design roles at major tech companies.

What job categories do people searching Google Asic Design Engineer jobs in Utah look for?

The top searched job categories for Google Asic Design Engineer jobs in Utah are:

What cities in Utah are hiring for Google Asic Design Engineer jobs?

Cities in Utah with the most Google Asic Design Engineer job openings:

Infographic showing various Google Asic Design Engineer job openings in Utah as of August 2026, with employment types broken down into 6% As Needed, 72% Full Time, and 22% Contract. Highlights an 94% In-person, and 6% Remote job distribution, with an average salary of $136,734 per year, or $65.7 per hour.

On-Site Rad-Hard Electrical Engineer (Hill AFB, Utah) with Security Clearance

Johns Hopkins University Applied Physics Laboratory

Hill Air Force Base, UT • On-site

Other

Medical, Dental, Vision, Life, Retirement, PTO

Re-posted 8 days ago


Job description

Description Do you want an exciting opportunity to represent APL on-site at Hill AFB on a significant program of national importance while working directly with Sponsors, industry peers and other APL team members? Do you have a passion for working in a fast-paced, high impact environment with a focus on rad-hard electronics? If so, we're looking for someone like you to join our team at APL. We are seeking an electrical engineer to help evaluate the Sentinel strategic missile system. This will be an on-site position, working at Hill Air Force base alongside other on-site APL personnel, our government sponsor, other government mission partners, and the Sentinel contractor. As an On-Site Rad-Hard Electrical Engineer... * Your primary responsibility is to serve as part of APL's HAFB-based team supporting the Sentinel program, enhancing APL's ability as an organization to support our government sponsor. In doing so, you will maintain regular communications with APL's program and project managers, line-side leaders and organizations in Laurel, and fellow members of the APL on-site technical team to increase awareness of Sentinel activities, developments, decisions, areas of concern, and opportunities where APL can help the Sentinel program.
* You will interface directly with the sponsor to understand their needs, and work with APL's Sentinel key leaders and fellow members of APL's on-site technical team to recommend, support, and execute work in support of the Sentinel Program Office's desire to "own the technical baseline."
* You will serve as a technical advisor and subject matter expert to the government for guidance hardware with a focus on rad-hard components. This includes communicating progress on the guidance computer along with other guidance hardware and acting as a liaison between the government and the APL home campus team.
* You will Identify and collect information needed to perform credible analysis of system level effects.
* You will support instrument and system level design reviews as well as guidance hardware meetings.
* You will expand your technical skillset to include additional nuclear hardness and survivability areas.
* You and the team of other APL SMEs at Hill AFB will collaborate to provide unique analyses of the Sentinel WS from a systems-level viewpoint. Qualifications You meet our minimum qualifications for the job if you... * Have a B.S. in Electrical Engineering or Physics (or closely related technical field), with 2+ of relevant technical professional experience.
* Have experience in electronic design and ability to review design information for the sponsor.
* Are familiar with radiation environments and the principles of radiation interactions with matter.
* Are able to effectively shape the day-to-day tasking to meet sponsor needs, multi-task, and adapt to changing demands with minimal guidance.
* Have exceptionally strong interpersonal, communication, and leadership skills, and ability to interface with senior military and civil service personnel.
* Are willing to relocate to Utah in the vicinity of Hill AFB, with periodic travel to APL, contractor sites, and to other locations. * Are willing and able to travel occasionally (potentially 5-6 trips per year of duration one week or less, including travel back to the APL Laurel campus).
* Hold an active Secret security clearance and are able to obtain a Top Secret/SCI level clearance. If selected, you will be subject to a government security investigation and must meet the requirements for access to classified information. Eligibility requirements include U.S. citizenship.
You 'll go above and beyond our minimum requirements if you... * Have an M.S. (or above) in Electrical Engineering or Physics (or closely related technical field) and/or 5+ years of rad-hard electronics.
* Have experience with and ability to communicate to sponsors ASIC design flow/fabrication process.
* Have experience with and ability to communicate to sponsors printed wiring board (PWB) design/fabrication process.
* Have experience with SPICE modeling.
* Have experience with radiation effects on electronics testing (dose and dose rate for x-rays, gamma rays, neutrons, protons, and heavy ions). * Have experience with radiation hardened electronics for strategic weapon systems.
* Are familiar with the natural space environment.
* Are familiar with nuclear weapon environments and their effects on systems.
* Have radiation detection experience.
* Are a proven thought leader with sponsor engagement experience.
* Currently hold an active Top Secret clearance (or above). About Us Why Work at APL? The Johns Hopkins University Applied Physics Laboratory (APL) brings world-class expertise to our nation's most critical defense, security, space and science challenges. While we are dedicated to solving complex challenges and pioneering new technologies, what makes us truly outstanding is our culture. We offer a vibrant, welcoming atmosphere where you can bring your authentic self to work, continue to grow, and build strong connections with inspiring teammates. At APL, we celebrate our differences of perspectives and encourage creativity and bold, new ideas. Our employees enjoy generous benefits, including a robust education assistance program, unparalleled retirement contributions, and a healthy work/life balance. APL's campus is located in the Baltimore-Washington metro area. Learn more about our career opportunities at https://www.jhuapl.edu/careers. All qualified applicants will receive consideration for employment without regard to race, creed, color, religion, sex, gender identity or expression, sexual orientation, national origin, age, physical or mental disability, genetic information, veteran status, occupation, marital or familial status, political opinion, personal appearance, or any other characteristic protected by applicable law. APL is committed to providing reasonable accommodation to individuals of all abilities, including those with disabilities. If you require a reasonable accommodation to participate in any part of the hiring process, please contact . The referenced pay range is based on JHU APL's good faith belief at the time of posting. Actual compensation may vary based on factors such as geographic location, work experience, market conditions, education/training and skill level with consideration for internal parity. For salaried employees scheduled to work less than 40 hours per week, annual salary will be prorated based on the number of hours worked. APL may offer bonuses or other forms of compensation per internal policy and/or contractual designation. Additional compensation may be provided in the form of a sign-on bonus, relocation benefits, locality allowance or discretionary payments for exceptional performance. APL provides eligible staff with a comprehensive benefits package including retirement plans, paid time off, medical, dental, vision, life insurance, short-term disability, long-term disability, flexible spending accounts, education assistance, and training and development. Applications are accepted on a rolling basis. Minimum Rate $100,000 Annually Maximum Rate $245,000 Annually