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Google Asic Design Engineer Jobs in Riverside, CA

Broadcom

ASIC Design Engineer

Irvine, CA

$108K - $172K/yr

We are looking for an ASIC Implementation Engineer with demonstrated expertise in multiple disciplines including synthesis, design for test, floorplanning, place and route, clock methodology, power ...

Broadcom, Inc.

ASIC Design Engineer

Irvine, CA · On-site

$108K - $172K/yr

We are looking for an ASIC Implementation Engineer with demonstrated expertise in multiple disciplines including synthesis, design for test, floorplanning, place and route, clock methodology, power ...

Broadcom

ASIC Design Engineer

Irvine, CA · On-site

$127K - $203K/yr

We are looking for an ASIC Implementation Engineer with demonstrated expertise in multiple disciplines including synthesis, design for test, floorplanning, place and route, clock methodology, power ...

Broadcom, Inc.

ASIC Design Engineer

Irvine, CA · On-site

$127K - $203K/yr

We are looking for an ASIC Implementation Engineer with demonstrated expertise in multiple disciplines including synthesis, design for test, floorplanning, place and route, clock methodology, power ...

Phizenix

Digital Design Engineer

Irvine, CA · On-site

$180K - $250K/yr

: Role Overview We are seeking an ASIC Design Engineer to own digital design, integration, and bring-up for production-grade high-speed interconnect silicon. You will translate micro-architecture into ...

OMNIVISION

Sr. Digital Design Engineer

Irvine, CA

We are looking for Digital Design Engineer for design and development of next generation image ... In depth hands-on experience in ASIC design flow: RTL coding, simulation, synthesis, static timing ...

OMNIVISION

Sr. Digital Design Engineer

Irvine, CA · On-site

$120K - $150K/yr

Description We are looking for Digital Design Engineer for design and development of next ... In depth hands-on experience in ASIC design flow: RTL coding, simulation, synthesis, static timing ...

OMNIVISION

Sr. Digital Design Engineer

Irvine, CA

$120K - $150K/yr

We are looking for Digital Design Engineer for design and development of next generation image ... In depth hands-on experience in ASIC design flow: RTL coding, simulation, synthesis, static timing ...

Purple Hires Inc

ASIC DFT Engineer

Irvine, CA · On-site

... Lead ASIC DFT Engineer to architect, implement, verify, and debug advanced DFT solutions for ... Collaborate with RTL design, verification, physical design, STA, and silicon validation teams to ...

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All JobsGoogle Asic Design Engineer JobsGoogle Asic Design Engineer Jobs in Riverside, CA

Google Asic Design Engineer information

See Riverside, CA salary details

$98.1K

$156.7K

$210.7K

How much do google asic design engineer jobs pay per year?

As of Jul 31, 2026, the average yearly pay for google asic design engineer in Riverside, CA is $156,694.00, according to ZipRecruiter salary data. Most workers in this role earn between $137,200.00 and $187,800.00 per year, depending on experience, location, and employer.

What is the difference between Google Asic Design Engineer vs Google FPGA Design Engineer?

AspectGoogle Asic Design EngineerGoogle FPGA Design Engineer
Required CredentialsBachelor's/Master's in Electrical Engineering or Computer Engineering; experience in ASIC designBachelor's/Master's in Electrical Engineering or Computer Engineering; FPGA design experience
Work EnvironmentDesigning custom silicon chips for Google productsDeveloping and testing FPGA prototypes for hardware acceleration
Employer & Industry UsagePrimarily in semiconductor and hardware design teams at GoogleHardware prototyping and acceleration teams at Google

The main difference between a Google Asic Design Engineer and a Google FPGA Design Engineer lies in their focus: ASIC engineers design custom chips for optimized performance, while FPGA engineers develop flexible hardware prototypes using field-programmable gate arrays. Both roles require strong electrical engineering skills but serve different stages of hardware development.

How does a Google ASIC Design Engineer typically collaborate with cross-functional teams during the chip development process?

As a Google ASIC Design Engineer, you will work closely with teams such as architecture, verification, software, and hardware validation to ensure successful chip delivery. Collaboration often involves regular meetings to align on design specifications, resolve integration issues, and discuss performance optimization. Effective communication is essential, as you’ll need to translate requirements from system architects into detailed hardware designs and provide feedback to verification and validation teams. This cross-functional interaction fosters a dynamic work environment and helps ensure the final product meets Google's rigorous standards.

What does a Google ASIC Design Engineer do?

A Google ASIC Design Engineer is responsible for designing and developing custom integrated circuits, known as Application-Specific Integrated Circuits (ASICs), that power Google's data centers, cloud infrastructure, and consumer devices. Their work involves collaborating with cross-functional teams to define requirements, create architecture, perform logic and physical design, and validate the silicon before production. They use advanced design tools and methodologies to ensure high performance, low power consumption, and reliability. Ultimately, their contributions help improve the efficiency and capabilities of Google's hardware products.

What are the key skills and qualifications needed to thrive as a Google ASIC Design Engineer, and why are they important?

To thrive as a Google ASIC Design Engineer, you need a strong background in electrical engineering, digital logic design, and experience with ASIC development, typically backed by a relevant degree. Familiarity with hardware description languages (such as Verilog or VHDL), EDA tools (like Synopsys or Cadence), and an understanding of SoC architectures are essential, and related certifications can be valuable. Strong problem-solving skills, attention to detail, and effective teamwork and communication abilities help set candidates apart. These skills are crucial for designing reliable, high-performance ASICs that meet Google's specifications and project timelines.
What job categories do people searching Google Asic Design Engineer jobs in Riverside, CA look for? The top searched job categories for Google Asic Design Engineer jobs in Riverside, CA are:
What cities near Riverside, CA are hiring for Google Asic Design Engineer jobs? Cities near Riverside, CA with the most Google Asic Design Engineer job openings:
Google Asic Design Engineer jobs near you
Infographic showing various Google Asic Design Engineer job openings in Riverside, CA as of July 2026, with employment types broken down into 84% Full Time, 8% Part Time, and 8% Contract. Highlights an 100% In-person job distribution, with an average salary of $156,694 per year, or $75.3 per hour.

ASIC Design Engineer

Broadcom

Irvine, CA

$108K - $172K/yr

Full-time

Medical, Dental, Vision, Retirement, PTO

Re-posted 29 days ago

Broadcom rating

8.7

Company rating: 8.7 out of 10

Based on 23 frontline employees who took The Breakroom Quiz

19th of 156 rated electronics manufacturers

Job description

Please Note:

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Job Description:

We are looking for an ASIC Implementation Engineer with demonstrated expertise in multiple disciplines including synthesis, design for test, floorplanning, place and route, clock methodology, power planning and analysis, timing closure, signal integrity and physical design checks.

Responsibilities Include:

  • Participate in large complex design implementations using the latest technology nodes; lead one or more disciplines in design closure as part of the design team.

  • Have expertise in multiple EDA vendor solutions and be able to quickly adapt to changing requirements.

  • Participate and drive peer reviews to ensure all quality requirements are met.

  • Work with customers and design teams across multiple geographies.

Job Complexity/Supervision:

  • Ability to work on complex technical projects.

  • Exercises judgement in selecting methods, techniques and evaluation criteria for obtaining results.

  • Complete tasks with little supervision, able to lead projects and set direction for other project members.

Experience:

  • Bachelor's degree in Electrical Engineering or related field and 8+ years of related experience or Masters degree in Electrical Engineering or related field and 6+ years of related experience

Additional Job Description:

Compensation and Benefits

The annual base salary range for this position is$108,000 - $172,800.

As a valued member of our team, you'll be eligible for a discretionary annual bonus and the opportunity to receive not only a competitive new hire equity grant, but also annual equity awards, connecting your success directly to the company's growth. All subject to relevant plan documents and award agreements.

Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.

Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.

If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.

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