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Google Asic Design Engineer Jobs in Riverside, CA

SR. ASIC DESIGN ENGINEER (STARSHIELD) Starshield leverages SpaceX's Starlink technology and launch capability to support national security efforts. While Starlink is designed for consumer and ...

As an ASIC Design Engineer on the Starshield team, you will be working on advanced development programs in support of U.S. National Security. In this role, you will be developing cutting-edge next ...

ASIC Design Engineer

Irvine, CA · On-site

$108K - $172K/yr

We are looking for an ASIC Implementation Engineer with demonstrated expertise in multiple disciplines including synthesis, design for test, floorplanning, place and route, clock methodology, power ...

ASIC Design Engineer

Irvine, CA · On-site

$108K - $172K/yr

We are looking for an ASIC Implementation Engineer with demonstrated expertise in multiple disciplines including synthesis, design for test, floorplanning, place and route, clock methodology, power ...

ASIC Design Engineer

Irvine, CA · On-site

$127K - $203K/yr

We are looking for an ASIC Implementation Engineer with demonstrated expertise in multiple disciplines including synthesis, design for test, floorplanning, place and route, clock methodology, power ...

ASIC Design Engineer

Irvine, CA · On-site

$127K - $203K/yr

We are looking for an ASIC Implementation Engineer with demonstrated expertise in multiple disciplines including synthesis, design for test, floorplanning, place and route, clock methodology, power ...

Sr. ASIC RTL Design Engineer

Irvine, CA · On-site

$150K - $250K/yr

Sr. ASIC RTL Design Engineer Job Title: Sr. ASIC RTL Design Engineer Job Location: San Jose, CA or Irvine, CA Compensation: $150K - $250K base DOE plus equity Requirements: Logic Design, RTL ...

New

Sr. Digital Design Engineer

Irvine, CA · On-site

$120K - $150K/yr

We are looking for Digital Design Engineer for design and development of next generation image ... In depth hands-on experience in ASIC design flow: RTL coding, simulation, synthesis, static timing ...

Sr. Digital Design Engineer

Irvine, CA · On-site

$120K - $150K/yr

Description We are looking for Digital Design Engineer for design and development of next ... In depth hands-on experience in ASIC design flow: RTL coding, simulation, synthesis, static timing ...

We are looking for Digital Design Engineer for design and development of next generation image ... In depth hands-on experience in ASIC design flow: RTL coding, simulation, synthesis, static timing ...

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Showing results 1-20

Google Asic Design Engineer information

See Riverside, CA salary details

$98.1K

$156.7K

$210.7K

How much do google asic design engineer jobs pay per year?

As of Jul 9, 2026, the average yearly pay for google asic design engineer in Riverside, CA is $156,694.00, according to ZipRecruiter salary data. Most workers in this role earn between $137,200.00 and $187,800.00 per year, depending on experience, location, and employer.

What is the difference between Google Asic Design Engineer vs Google FPGA Design Engineer?

AspectGoogle Asic Design EngineerGoogle FPGA Design Engineer
Required CredentialsBachelor's/Master's in Electrical Engineering or Computer Engineering; experience in ASIC designBachelor's/Master's in Electrical Engineering or Computer Engineering; FPGA design experience
Work EnvironmentDesigning custom silicon chips for Google productsDeveloping and testing FPGA prototypes for hardware acceleration
Employer & Industry UsagePrimarily in semiconductor and hardware design teams at GoogleHardware prototyping and acceleration teams at Google

The main difference between a Google Asic Design Engineer and a Google FPGA Design Engineer lies in their focus: ASIC engineers design custom chips for optimized performance, while FPGA engineers develop flexible hardware prototypes using field-programmable gate arrays. Both roles require strong electrical engineering skills but serve different stages of hardware development.

How does a Google ASIC Design Engineer typically collaborate with cross-functional teams during the chip development process?

As a Google ASIC Design Engineer, you will work closely with teams such as architecture, verification, software, and hardware validation to ensure successful chip delivery. Collaboration often involves regular meetings to align on design specifications, resolve integration issues, and discuss performance optimization. Effective communication is essential, as you’ll need to translate requirements from system architects into detailed hardware designs and provide feedback to verification and validation teams. This cross-functional interaction fosters a dynamic work environment and helps ensure the final product meets Google's rigorous standards.

What does a Google ASIC Design Engineer do?

A Google ASIC Design Engineer is responsible for designing and developing custom integrated circuits, known as Application-Specific Integrated Circuits (ASICs), that power Google's data centers, cloud infrastructure, and consumer devices. Their work involves collaborating with cross-functional teams to define requirements, create architecture, perform logic and physical design, and validate the silicon before production. They use advanced design tools and methodologies to ensure high performance, low power consumption, and reliability. Ultimately, their contributions help improve the efficiency and capabilities of Google's hardware products.

What are the key skills and qualifications needed to thrive as a Google ASIC Design Engineer, and why are they important?

To thrive as a Google ASIC Design Engineer, you need a strong background in electrical engineering, digital logic design, and experience with ASIC development, typically backed by a relevant degree. Familiarity with hardware description languages (such as Verilog or VHDL), EDA tools (like Synopsys or Cadence), and an understanding of SoC architectures are essential, and related certifications can be valuable. Strong problem-solving skills, attention to detail, and effective teamwork and communication abilities help set candidates apart. These skills are crucial for designing reliable, high-performance ASICs that meet Google's specifications and project timelines.
What are popular job titles related to Google Asic Design Engineer jobs in Riverside, CA? For Google Asic Design Engineer jobs in Riverside, CA, the most frequently searched job titles are:
What job categories do people searching Google Asic Design Engineer jobs in Riverside, CA look for? The top searched job categories for Google Asic Design Engineer jobs in Riverside, CA are:
What cities near Riverside, CA are hiring for Google Asic Design Engineer jobs? Cities near Riverside, CA with the most Google Asic Design Engineer job openings:
Infographic showing various Google Asic Design Engineer job openings in Riverside, CA as of July 2026, with employment types broken down into 84% Full Time, 8% Part Time, and 8% Contract. Highlights an 100% In-person job distribution, with an average salary of $156,694 per year, or $75.3 per hour.
Principal ASIC Design Engineer (Starshield)

Principal ASIC Design Engineer (Starshield)

SpaceX

Irvine, CA • On-site

$200K - $285K/yr

Other

Medical, Dental, Vision, Life, Retirement, PTO

Posted 6 days ago


SpaceX rating

8.7

Company rating: 8.7 out of 10

Based on 144 frontline employees who took The Breakroom Quiz

13th of 61 rated aerospace companies


Job description

PRINCIPAL ASIC DESIGN ENGINEER (STARSHIELD)

Starshield leverages SpaceX's Starlink technology and launch capability to support national security efforts. While Starlink is designed for consumer and commercial use, Starshield is designed for government use, with an initial focus on earth observation, communications, and hosted payloads. As an ASIC Design Engineer on the Starshield team, you will be working on advanced development programs in support of U.S. National Security. In this role, you will be developing cutting-edge next-generation FPGAs and ASICs for deployment in space and ground infrastructures around the globe. You will work in a highly collaborative and fast-paced environment, where we are exploring unsolved problems and applying the SpaceX mindset of iterating rapidly to go from design and demo to operational capability at lightning pace.

RESPONSIBILITIES:

  • Design digital ASICs and/or FPGAs for Starshield projects.
  • Evaluate architectural trade-offs based on features, performance requirements and system limitations. Derive specifications for the subsystems and circuits, and work with modem/DSP and RFIC engineers to partition functions between hardware and software domains.
  • Define micro-architecture, implement the RTL in Verilog/System Verilog, integrate that in top level and deliver the fully verified, synthesis/timing clean design.
  • Work closely with verification team to ensure all aspects of the design are covered and verified.
  • Provide timing constraints for those IPs and support the physical implementation team (synthesis, timing closure, formality check).
  • Participate in silicon bring-up and validation. Assist in the development of automated test lab equipment for lab measurements.

BASIC QUALIFICATIONS:

  • Bachelor's degree in electrical engineering, computer engineering, or computer science.
  • 8+ years of experience in RTL implementation and/or FPGA/ASIC development.

PREFERRED SKILLS AND EXPERIENCE:

  • Experience solving problems including clock domain crossings and power optimization.
  • Experience developing complex ASICs.
  • Experience with multicore CPU subsystem design.
  • Experience with standard bus protocols (e.g. AXI, AHB, etc.).
  • Experience with embedded processors.
  • Experience with high speed and low power design techniques.
  • Scripting skills (Python, TCL etc.).
  • Experience with EDA tools such as HDL simulators (e.g. VCS, Questa, IES), HDL Lint tools (e.g. Spyglass) and FPGA tools (e.g. Xilinx Vivado, Altera Quartus II).
  • Ability to work in a dynamic environment with changing needs and requirements.
  • Team-player, can-do attitude and ability to work well in a group environment while still contributing on an individual basis.
  • Enjoy being challenged and learning new skills.

ADDITIONAL REQUIREMENTS:

  • Ability to work long hours and weekends as necessary to support critical milestones.
  • Willingness to travel for off-site testing.
  • An active TS-SCI clearance may provide the opportunity for you to work on sensitive SpaceX missions; if so, you will be subject to pre-employment drug and random drug and alcohol testing.

COMPENSATION AND BENEFITS:    

Pay range:    
Principal ASIC Design Engineer: $200,000.00 - $285,000.00/per year    

Your actual level and base salary will be determined on a case-by-case basis and may vary based on the following considerations: job-related knowledge and skills, education, and experience. Those with an active clearance will receive a 10% differential, up to an additional $15,000 annually, once officially briefed into a classified program.

Base salary is just one part of your total rewards package at SpaceX. You may also be eligible for long-term incentives, in the form of company stock, stock options, or long-term cash awards, as well as potential discretionary bonuses and the ability to purchase additional stock at a discount through an Employee Stock Purchase Plan. You will also receive access to comprehensive medical, vision, and dental coverage, access to a 401(k) retirement plan, short and long-term disability insurance, life insurance, paid parental leave, and various other discounts and perks. You may also accrue 3 weeks of paid vacation and will be eligible for 10 or more paid holidays per year. Employees accrue paid sick leave pursuant to Company policy which satisfies or exceeds the accrual, carryover, and use requirements of the law.


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