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Google Asic Design Engineer Jobs in Riverside, CA

SpaceX

Sr. ASIC Design Engineer (Starshield)

Irvine, CA · On-site

$160K - $225K/yr

As an ASIC Design Engineer on the Starshield team, you will be working on advanced development programs in support of U.S. National Security. In this role, you will be developing cutting-edge next ...

Broadcom

ASIC Design Engineer

Irvine, CA

$108K - $172K/yr

We are looking for an ASIC Implementation Engineer with demonstrated expertise in multiple disciplines including synthesis, design for test, floorplanning, place and route, clock methodology, power ...

Broadcom, Inc.

ASIC Design Engineer

Irvine, CA · On-site

$108K - $172K/yr

We are looking for an ASIC Implementation Engineer with demonstrated expertise in multiple disciplines including synthesis, design for test, floorplanning, place and route, clock methodology, power ...

Broadcom

ASIC Design Engineer

Irvine, CA

$127K - $203K/yr

We are looking for an ASIC Implementation Engineer with demonstrated expertise in multiple disciplines including synthesis, design for test, floorplanning, place and route, clock methodology, power ...

Broadcom, Inc.

ASIC Design Engineer

Irvine, CA · On-site

$127K - $203K/yr

We are looking for an ASIC Implementation Engineer with demonstrated expertise in multiple disciplines including synthesis, design for test, floorplanning, place and route, clock methodology, power ...

OMNIVISION

Sr. Digital Design Engineer

Irvine, CA

$120K - $150K/yr

We are looking for Digital Design Engineer for design and development of next generation image ... In depth hands-on experience in ASIC design flow: RTL coding, simulation, synthesis, static timing ...

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All JobsGoogle Asic Design Engineer JobsGoogle Asic Design Engineer Jobs in Riverside, CA

Google Asic Design Engineer information

See Riverside, CA salary details

$98.1K

$156.7K

$210.7K

How much do google asic design engineer jobs pay per year?

As of Jun 16, 2026, the average yearly pay for google asic design engineer in Riverside, CA is $156,694.00, according to ZipRecruiter salary data. Most workers in this role earn between $137,200.00 and $187,800.00 per year, depending on experience, location, and employer.

What is the difference between Google Asic Design Engineer vs Google FPGA Design Engineer?

AspectGoogle Asic Design EngineerGoogle FPGA Design Engineer
Required CredentialsBachelor's/Master's in Electrical Engineering or Computer Engineering; experience in ASIC designBachelor's/Master's in Electrical Engineering or Computer Engineering; FPGA design experience
Work EnvironmentDesigning custom silicon chips for Google productsDeveloping and testing FPGA prototypes for hardware acceleration
Employer & Industry UsagePrimarily in semiconductor and hardware design teams at GoogleHardware prototyping and acceleration teams at Google

The main difference between a Google Asic Design Engineer and a Google FPGA Design Engineer lies in their focus: ASIC engineers design custom chips for optimized performance, while FPGA engineers develop flexible hardware prototypes using field-programmable gate arrays. Both roles require strong electrical engineering skills but serve different stages of hardware development.

How does a Google ASIC Design Engineer typically collaborate with cross-functional teams during the chip development process?

As a Google ASIC Design Engineer, you will work closely with teams such as architecture, verification, software, and hardware validation to ensure successful chip delivery. Collaboration often involves regular meetings to align on design specifications, resolve integration issues, and discuss performance optimization. Effective communication is essential, as you’ll need to translate requirements from system architects into detailed hardware designs and provide feedback to verification and validation teams. This cross-functional interaction fosters a dynamic work environment and helps ensure the final product meets Google's rigorous standards.

What does a Google ASIC Design Engineer do?

A Google ASIC Design Engineer is responsible for designing and developing custom integrated circuits, known as Application-Specific Integrated Circuits (ASICs), that power Google's data centers, cloud infrastructure, and consumer devices. Their work involves collaborating with cross-functional teams to define requirements, create architecture, perform logic and physical design, and validate the silicon before production. They use advanced design tools and methodologies to ensure high performance, low power consumption, and reliability. Ultimately, their contributions help improve the efficiency and capabilities of Google's hardware products.

What are the key skills and qualifications needed to thrive as a Google ASIC Design Engineer, and why are they important?

To thrive as a Google ASIC Design Engineer, you need a strong background in electrical engineering, digital logic design, and experience with ASIC development, typically backed by a relevant degree. Familiarity with hardware description languages (such as Verilog or VHDL), EDA tools (like Synopsys or Cadence), and an understanding of SoC architectures are essential, and related certifications can be valuable. Strong problem-solving skills, attention to detail, and effective teamwork and communication abilities help set candidates apart. These skills are crucial for designing reliable, high-performance ASICs that meet Google's specifications and project timelines.
What job categories do people searching Google Asic Design Engineer jobs in Riverside, CA look for? The top searched job categories for Google Asic Design Engineer jobs in Riverside, CA are:
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Google Asic Design Engineer jobs near you

ASIC Design Engineer - Staff

Celero Communications, Inc.

Irvine, CA • On-site

$150K - $250K/yr

Full-time

Posted 10 days ago

Job description

About the Role:
Celero Communication Inc. is an exciting and fast-growing start-up in the semiconductor industry, pushing boundaries with innovative technologies that power the world's most advanced AI and data center infrastructure.
Celero is seeking skilled and motivated ASIC Design Engineers to join our team and contribute to the development of optical transceivers for next-generation optical modems. The ideal candidate will play a crucial role in designing and developing ASICs for cutting-edge technologies.
Locations: Irvine, CA | San Jose, CA | Ottawa, ON, Canada | Vancouver, BC, Canada
Key Responsibilities:
  • Design and implement digital circuits using HDL (Verilog/ System Verilog).
  • Perform synthesis, timing analysis, Lint, formal equivalence, Clock Domain Crossing (CDC) analysis
  • Optimize designs for performance, power, and area (PPA) requirements.
  • Perform RTL simulation and verification to ensure design functionality.
  • Participate in design reviews and provide technical guidance to team members.
  • Collaborate with cross-functional teams on system integration and validation.

Qualifications:
  • Bachelor's or higher degree in Electrical Engineering, Computer Engineering, or a related field.
  • 3+ years of experience in digital design and verification.
  • Proficiency in HDLs such as Verilog, or System Verilog.
  • Strong understanding of digital design principles and methodologies.
  • Familiarity with ASIC design flow, and experience with ASIC design tools.
  • Knowledge of low-power design techniques.
  • Familiarity with verification methodologies (e.g., UVM, formal verification).
  • Excellent problem-solving, strong communication and teamwork skills.

Preferred Skills
  • Strong knowledge of Digital Signal Processing (DSP), Digital Communication, and Forward Error Correction (FEC) techniques.
  • Experience with scripting languages (e.g., Python, Tcl).
  • Understanding of Optical Communication Standards is a plus.
  • Ability to multitask and adapt to a fast-paced, dynamic environment.

Salary Range
$150,000 - $250,000 Base Annually
The final offer will be determined based on job-related skills, experience, qualifications, and location.

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