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Google Asic Design Engineer Jobs in Riverside, CA

Broadcom, Inc.

ASIC Design Verification Engineer

Irvine, CA · On-site

$129K - $207K/yr

We are looking for highly skilled and efficient Constrained Random Design Verification engineers that want to verify new designs that can evolve rapidly at every generation in a very dynamic market ...

Silvus Technologies

FPGA Design Engineer

Irvine, CA · On-site

$132K - $181K/yr

FPGA Design Engineers are responsible for the efficient implementation of novel signal processing ... Experience with communication systems on FPGA or ASIC designs. WORKING CONDITIONS AND PHYSICAL ...

OmniVision Technologies

Analog Design Engineer

Irvine, CA · On-site

$125K - $135K/yr

... asic_pixel array, column-amplifier, comparator, ramp generator, ASRAM and XDEC by using Cadence ... Collaborate with Digital Engineer to define and design the analog to digital interface; Collaborate ...

OMNIVISION

Analog Design Engineer

Irvine, CA · On-site

... asic_pixel array, column-amplifier, comparator, ramp generator, ASRAM and XDEC by using Cadence ... Collaborate with Digital Engineer to define and design the analog to digital interface; Collaborate ...

OMNIVISION

Analog Design Engineer

Irvine, CA · On-site

$125K - $135K/yr

... asic_pixel array, column-amplifier, comparator, ramp generator, ASRAM and XDEC by using Cadence ... Collaborate with Digital Engineer to define and design the analog to digital interface; Collaborate ...

OMNIVISION

Analog Design Engineer

Irvine, CA · On-site

$125K - $135K/yr

... asic_pixel array, column-amplifier, comparator, ramp generator, ASRAM and XDEC by using Cadence ... Collaborate with Digital Engineer to define and design the analog to digital interface; Collaborate ...

Silvus Technologies

FPGA Design Engineer

Irvine, CA · On-site

$100K - $140K/yr

FPGA Design Engineers are responsible for the efficient implementation of novel signal processing ... Experience with communication systems on FPGA or ASIC designs. WORKING CONDITIONS AND PHYSICAL ...

Apple

PHY RTL Design Engineer

Irvine, CA · On-site

... engineering team spanning RF/Analog architecture, and design, Systems/PHY/MAC architecture and design, VLSI/RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW ...

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All JobsGoogle Asic Design Engineer JobsGoogle Asic Design Engineer Jobs in Riverside, CA

Google Asic Design Engineer information

See Riverside, CA salary details

$98.1K

$156.7K

$210.7K

How much do google asic design engineer jobs pay per year?

As of Sep 10, 2026, the average yearly pay for google asic design engineer in Riverside, CA is $156,694.00, according to ZipRecruiter salary data. Most workers in this role earn between $137,200.00 and $187,800.00 per year, depending on experience, location, and employer.

What does a Google ASIC Design Engineer do?

A Google ASIC Design Engineer is responsible for designing and developing custom integrated circuits, known as Application-Specific Integrated Circuits (ASICs), that power Google's data centers, cloud infrastructure, and consumer devices. Their work involves collaborating with cross-functional teams to define requirements, create architecture, perform logic and physical design, and validate the silicon before production. They use advanced design tools and methodologies to ensure high performance, low power consumption, and reliability. Ultimately, their contributions help improve the efficiency and capabilities of Google's hardware products.

How does a Google ASIC Design Engineer typically collaborate with cross-functional teams during the chip development process?

As a Google ASIC Design Engineer, you will work closely with teams such as architecture, verification, software, and hardware validation to ensure successful chip delivery. Collaboration often involves regular meetings to align on design specifications, resolve integration issues, and discuss performance optimization. Effective communication is essential, as you’ll need to translate requirements from system architects into detailed hardware designs and provide feedback to verification and validation teams. This cross-functional interaction fosters a dynamic work environment and helps ensure the final product meets Google's rigorous standards.

What are the key skills and qualifications needed to thrive as a Google ASIC Design Engineer, and why are they important?

To thrive as a Google ASIC Design Engineer, you need a strong background in electrical engineering, digital logic design, and experience with ASIC development, typically backed by a relevant degree. Familiarity with hardware description languages (such as Verilog or VHDL), EDA tools (like Synopsys or Cadence), and an understanding of SoC architectures are essential, and related certifications can be valuable. Strong problem-solving skills, attention to detail, and effective teamwork and communication abilities help set candidates apart. These skills are crucial for designing reliable, high-performance ASICs that meet Google's specifications and project timelines.

What is the difference between Google Asic Design Engineer vs Google FPGA Design Engineer?

AspectGoogle Asic Design EngineerGoogle FPGA Design Engineer
Required CredentialsBachelor's/Master's in Electrical Engineering or Computer Engineering; experience in ASIC designBachelor's/Master's in Electrical Engineering or Computer Engineering; FPGA design experience
Work EnvironmentDesigning custom silicon chips for Google productsDeveloping and testing FPGA prototypes for hardware acceleration
Employer & Industry UsagePrimarily in semiconductor and hardware design teams at GoogleHardware prototyping and acceleration teams at Google

The main difference between a Google Asic Design Engineer and a Google FPGA Design Engineer lies in their focus: ASIC engineers design custom chips for optimized performance, while FPGA engineers develop flexible hardware prototypes using field-programmable gate arrays. Both roles require strong electrical engineering skills but serve different stages of hardware development.

Are Google ASIC Design Engineers in demand?

ASIC Design Engineers at Google are in high demand due to the growing need for specialized hardware acceleration and efficient chip designs in data centers and AI applications. Skills in digital design, verification, and hardware description languages like Verilog or VHDL are highly valued, and the role often requires experience with EDA tools and FPGA prototyping. The demand is expected to remain strong as companies continue to develop custom chips for performance and energy efficiency.

How much does a Google ASIC Design Engineer make?

A Google ASIC Design Engineer typically earns a base salary ranging from $120,000 to $200,000 annually, with total compensation often including bonuses and stock options. Compensation varies based on experience, location, and level within the company, and the role requires expertise in hardware design, verification, and EDA tools.

What is the salary of Google ASIC Design Engineer in Google?

The salary for a Google ASIC Design Engineer typically ranges from $120,000 to $200,000 annually, depending on experience, location, and level within the company. Compensation may also include bonuses, stock options, and benefits, reflecting industry standards for specialized hardware design roles at major tech companies.

What are popular job titles related to Google Asic Design Engineer jobs in Riverside, CA?

For Google Asic Design Engineer jobs in Riverside, CA, the most frequently searched job titles are:

What cities near Riverside, CA are hiring for Google Asic Design Engineer jobs?

Cities near Riverside, CA with the most Google Asic Design Engineer job openings:

Google Asic Design Engineer jobs near you
Infographic showing various Google Asic Design Engineer job openings in Riverside, CA as of September 2026, with employment types broken down into 1% Internship, 86% Full Time, 10% Part Time, and 3% Contract. Highlights an 81% Physical, 4% Hybrid, and 15% Remote job distribution, with an average salary of $156,694 per year, or $75.3 per hour.

Principal, IC Digital Design Engineer

Irvine, CA • On-site

Marvell Technology, Inc.
Manufacturing • 10K+ employees
Learn more about Marvell Technology, Inc.external

$146K/yr

Full-time

Life, Retirement

Re-posted 29 days ago

Job description

About Marvell
Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.
At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.
Your Team, Your Impact
As a Principal, Digital IC Design Engineer at Marvell, you will join the DCE - Connectivity Business Group, the team developing the high performance connectivity silicon that underpins AI scale data centers for the world's leading hyperscalers. Our group architects and implements advanced digital pipelines, high speed datapaths, and DSP driven processing engines that enable ultra high bandwidth, low latency data movement across next generation Ethernet and optical interconnects. You'll work closely with experts in architecture, verification, physical design, and systems to deliver complex ASICs that integrate cutting edge DSP algorithms, robust protocol handling, and PHY level innovations. This role offers the opportunity to shape foundational connectivity technologies, drive technical direction, and contribute to silicon solutions powering the global AI infrastructure.
What You Can Expect
  • Collaborate with systems and architecture teams to define SoC-level specifications, including performance, power, area, feature requirements, and DSP/datapath architectural considerations.
  • Translate high-level product and protocol requirements into detailed micro-architecture specifications for complex subsystems, high-speed datapaths, DSP pipelines, and IP blocks.
  • Own RTL development for assigned blocks, delivering high-quality, synthesizable SystemVerilog RTL that meets functionality, performance, and power targets.
  • Implement and drive the full ASIC front-end design flow, including lint, CDC/RDC, synthesis, timing constraint development, and design-for-test readiness.
  • Partner with STA and PNR teams to support timing closure, floorplanning, congestion analysis, and design optimizations across advanced process nodes.
  • Lead integration of digital logic into larger subsystems and top-level assemblies, ensuring clean interfaces, modularity, and reusability.
  • Develop scalable and maintainable design components, including parameterized datapaths, DSP building blocks, and reusable infrastructure logic.
  • Work closely with DV teams to define verification strategies, review test plans, and ensure functional, coverage-driven, and power-aware validation of the design.
  • Support pre-silicon validation, including emulation, FPGA prototyping, and performance modeling of high-speed datapaths and DSP algorithms.
  • Drive post-silicon bring-up and debug, collaborating with lab and systems teams to validate functionality, characterize performance, and resolve complex issues across datapath, DSP, and protocol layers.
  • Participate in detailed design and micro-architecture reviews, contributing to continuous improvement of design, verification, and methodology flows.

What We're Looking For
  • Extensive experience in digital ASIC design, including micro-architecture development, RTL implementation (SystemVerilog preferred), and integration of complex logic blocks.
  • 12+ years of industry experience working on large-scale ASICs for networking, data-center connectivity, or high-bandwidth compute architectures.
  • Strong background in high-performance DSP and high-speed datapath design, including pipelined arithmetic units, algorithm-driven hardware implementation, packet processing engines, memory subsystems, and large-scale control/state machines.
  • Familiarity with Ethernet protocols and networking standards, including MAC, PCS framing, flow control, and packet-level behaviors.
  • Proficiency with front-end design flows, including lint, CDC/RDC, synthesis, STA, and power/performance optimization.
  • Demonstrated ability to collaborate across architecture, verification, physical design, firmware, and systems teams, driving designs from concept through tape-out.
  • Strong debug skills across RTL simulation, emulation, FPGA prototypes, and silicon bring-up.
  • Familiarity with advanced process nodes (5nm, 3nm, or similar) and their implications for timing, power, and signal integrity.
  • Excellent communication and technical leadership skills, with the ability to influence design direction and drive execution.
  • BS/MS in Electrical Engineering, Computer Engineering, or related field; PhD is a plus.

Preferred / Plus Skills
  • Advanced high-speed DSP algorithm implementation, including adaptive equalization (FFE, DFE, CTLE), channel estimation, and high-throughput filtering architectures.
  • Experience with FEC architectures such as LDPC, RS, BCH, or other high-speed coding/decoding schemes used in networking and optical interconnects.
  • Previous PHY design experience, including PMA-level DSP pipelines, equalization blocks, clock recovery, and SerDes-adjacent logic.

Expected Base Pay Range (USD)
151,000 - 223,440, $ per annum
The successful candidate's starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.
Additional Compensation and Benefit Elements
Marvell is committed to providing exceptional, comprehensive benefits that support our employees at every stage - from internship to retirement and through life's most important moments. Our offerings are built around four key pillars: financial well-being, family support, mental and physical health, and recognition. Highlights include an employee stock purchase plan with a 2-year look back, family support programs to help balance work and home life, robust mental health resources to prioritize emotional well-being, and a recognition and service awards to celebrate contributions and milestones. We look forward to sharing more with you during the interview process.
All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.
Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at TAOps@marvell.com.
Interview Integrity
To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews.
These tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process.
This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment.
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