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Google Asic Design Engineer Jobs in Riverside, CA

Broadcom, Inc.

ASIC Design Verification Engineer

Irvine, CA · On-site

$91K - $152K/yr

We are looking for highly skilled and efficient Design Verification engineers that want to verify new designs that can evolve rapidly over the next several generations in a very dynamic market using ...

Apple

Debug SoC Design Engineer

Irvine, CA

$120K - $210K/yr

... integrated engineering team spanning RF/Analog architecture and design, Systems/PHY/MAC ... This is a highly visible role, where you will be at the center of the ASIC debug efforts ...

Apple

Debug SoC Design Engineer

Irvine, CA

$120K - $210K/yr

... integrated engineering team spanning RF/Analog architecture and design, Systems/PHY/MAC ... This is a highly visible role, where you will be at the center of the ASIC debug efforts ...

Apple

Debug SoC Design Engineer

Irvine, CA

$120K - $210K/yr

... integrated engineering team spanning RF/Analog architecture and design, Systems/PHY/MAC ... This is a highly visible role, where you will be at the center of the ASIC debug efforts ...

Apple

Debug SoC Design Engineer

Irvine, CA

$171K - $302K/yr

... integrated engineering team spanning RF/Analog architecture and design, Systems/PHY/MAC ... This is a highly visible role, where you will be at the center of the ASIC debug efforts ...

Apple

Debug SoC Design Engineer

Irvine, CA

$120K - $210K/yr

... integrated engineering team spanning RF/Analog architecture and design, Systems/PHY/MAC ... This is a highly visible role, where you will be at the center of the ASIC debug efforts ...

Apple

Debug SoC Design Engineer

Irvine, CA

$171K - $302K/yr

... integrated engineering team spanning RF/Analog architecture and design, Systems/PHY/MAC ... This is a highly visible role, where you will be at the center of the ASIC debug efforts ...

Apple

Debug SoC Design Engineer

Irvine, CA

$171K - $302K/yr

... integrated engineering team spanning RF/Analog architecture and design, Systems/PHY/MAC ... This is a highly visible role, where you will be at the center of the ASIC debug efforts ...

Apple

Debug SoC Design Engineer

Irvine, CA

$171K - $302K/yr

... integrated engineering team spanning RF/Analog architecture and design, Systems/PHY/MAC ... This is a highly visible role, where you will be at the center of the ASIC debug efforts ...

Apple

Debug SoC Design Engineer

Irvine, CA

$120K - $210K/yr

... integrated engineering team spanning RF/Analog architecture and design, Systems/PHY/MAC ... This is a highly visible role, where you will be at the center of the ASIC debug efforts ...

Apple

Debug SoC Design Engineer

Irvine, CA

$120K - $210K/yr

... integrated engineering team spanning RF/Analog architecture and design, Systems/PHY/MAC ... This is a highly visible role, where you will be at the center of the ASIC debug efforts ...

Silvus Technologies

FPGA Design Engineer

Irvine, CA

$132K - $181K/yr

FPGA Design Engineers are responsible for the efficient implementation of novel signal processing ... Experience with communication systems on FPGA or ASIC designs. WORKING CONDITIONS AND PHYSICAL ...

OMNIVISION

Analog Design Engineer

Irvine, CA

... asic_pixel array, column-amplifier, comparator, ramp generator, ASRAM and XDEC by using Cadence ... Collaborate with Digital Engineer to define and design the analog to digital interface; Collaborate ...

OMNIVISION

Analog Design Engineer

Irvine, CA

$125K - $135K/yr

... asic_pixel array, column-amplifier, comparator, ramp generator, ASRAM and XDEC by using Cadence ... Collaborate with Digital Engineer to define and design the analog to digital interface; Collaborate ...

OMNIVISION

Analog Design Engineer

Irvine, CA · On-site

$125K - $135K/yr

... asic_pixel array, column-amplifier, comparator, ramp generator, ASRAM and XDEC by using Cadence ... Collaborate with Digital Engineer to define and design the analog to digital interface; Collaborate ...

OmniVision Technologies

Analog Design Engineer

Irvine, CA · On-site

$125K - $135K/yr

... asic_pixel array, column-amplifier, comparator, ramp generator, ASRAM and XDEC by using Cadence ... Collaborate with Digital Engineer to define and design the analog to digital interface; Collaborate ...

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All JobsGoogle Asic Design Engineer JobsGoogle Asic Design Engineer Jobs in Riverside, CA

Google Asic Design Engineer information

See Riverside, CA salary details

$98.1K

$156.7K

$210.7K

How much do google asic design engineer jobs pay per year?

As of Jun 16, 2026, the average yearly pay for google asic design engineer in Riverside, CA is $156,694.00, according to ZipRecruiter salary data. Most workers in this role earn between $137,200.00 and $187,800.00 per year, depending on experience, location, and employer.

What is the difference between Google Asic Design Engineer vs Google FPGA Design Engineer?

AspectGoogle Asic Design EngineerGoogle FPGA Design Engineer
Required CredentialsBachelor's/Master's in Electrical Engineering or Computer Engineering; experience in ASIC designBachelor's/Master's in Electrical Engineering or Computer Engineering; FPGA design experience
Work EnvironmentDesigning custom silicon chips for Google productsDeveloping and testing FPGA prototypes for hardware acceleration
Employer & Industry UsagePrimarily in semiconductor and hardware design teams at GoogleHardware prototyping and acceleration teams at Google

The main difference between a Google Asic Design Engineer and a Google FPGA Design Engineer lies in their focus: ASIC engineers design custom chips for optimized performance, while FPGA engineers develop flexible hardware prototypes using field-programmable gate arrays. Both roles require strong electrical engineering skills but serve different stages of hardware development.

How does a Google ASIC Design Engineer typically collaborate with cross-functional teams during the chip development process?

As a Google ASIC Design Engineer, you will work closely with teams such as architecture, verification, software, and hardware validation to ensure successful chip delivery. Collaboration often involves regular meetings to align on design specifications, resolve integration issues, and discuss performance optimization. Effective communication is essential, as you’ll need to translate requirements from system architects into detailed hardware designs and provide feedback to verification and validation teams. This cross-functional interaction fosters a dynamic work environment and helps ensure the final product meets Google's rigorous standards.

What does a Google ASIC Design Engineer do?

A Google ASIC Design Engineer is responsible for designing and developing custom integrated circuits, known as Application-Specific Integrated Circuits (ASICs), that power Google's data centers, cloud infrastructure, and consumer devices. Their work involves collaborating with cross-functional teams to define requirements, create architecture, perform logic and physical design, and validate the silicon before production. They use advanced design tools and methodologies to ensure high performance, low power consumption, and reliability. Ultimately, their contributions help improve the efficiency and capabilities of Google's hardware products.

What are the key skills and qualifications needed to thrive as a Google ASIC Design Engineer, and why are they important?

To thrive as a Google ASIC Design Engineer, you need a strong background in electrical engineering, digital logic design, and experience with ASIC development, typically backed by a relevant degree. Familiarity with hardware description languages (such as Verilog or VHDL), EDA tools (like Synopsys or Cadence), and an understanding of SoC architectures are essential, and related certifications can be valuable. Strong problem-solving skills, attention to detail, and effective teamwork and communication abilities help set candidates apart. These skills are crucial for designing reliable, high-performance ASICs that meet Google's specifications and project timelines.
What job categories do people searching Google Asic Design Engineer jobs in Riverside, CA look for? The top searched job categories for Google Asic Design Engineer jobs in Riverside, CA are:
What cities near Riverside, CA are hiring for Google Asic Design Engineer jobs? Cities near Riverside, CA with the most Google Asic Design Engineer job openings:
Google Asic Design Engineer jobs near you
ASIC Design Verification Engineer

ASIC Design Verification Engineer

Broadcom, Inc.

Irvine, CA • On-site

$91K - $152K/yr

Full-time

Medical, Dental, Vision, Retirement, PTO

Posted 26 days ago

Broadcom rating

8.7

Company rating: 8.7 out of 10

Based on 23 frontline employees who took The Breakroom Quiz

11th of 139 rated electronics manufacturers

Job description

Please Note:
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Job Description:
We are looking for highly skilled and efficient Design Verification engineers that want to verify new designs that can evolve rapidly over the next several generations in a very dynamic market using industry proven constrained random methodologies with System Verilog and UVM. You can become a member of an extremely skilled and efficient group of engineers working on PCIe and other host interfaces. The technology is constantly evolving and this provides a chance to work on leading edge technology that is also used in other product lines.
This is a rare opportunity to be part of a successful product line. All aspects of Design Verification will be involved, along with opportunities for technical leadership.
Skills: Self motivated personality with a strong presence to do things right. Need to have a strong sense of teamwork and ability to work well with others. Constrained random verification methodologies with experience driving completion via coverage closure. Preferable to have skills with SV and UVM, well versed in OOP. Experience with PCIe and experience with using 3rd party BFM is a strong plus. Looking for candidates with a good understanding of datapath flows.
Tools/Languages: System Verilog (TB structures - Class, SVA, etc.), UVM, VCS, Incisive, Scripting skills a + (Python, Perl, ...)
Experience: BSEE + 8+ years of related experience, or MSEE + 6+ years of experience
Be part of developing our next generation product in a series of high throughput Ethernet products that deliver unprecedented performance at critically important power efficiency.
Additional Job Description:
Compensation and Benefits
The annual base salary range for this position is $91,200 - $152,000
This position is also eligible for a discretionary annual bonus in accordance with relevant plan documents, and equity in accordance with equity plan documents and equity award agreements.
Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.
Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.
If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.

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