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Google Asic Design Engineer Jobs in Riverside, CA

Broadcom Inc.

ASIC Design Verification Engineer

Irvine, CA · On-site

$91.20 - $152/hr

Overview Broadcom is seeking experienced Design Verification engineers to work on PCIe and host interface technologies. The role involves verifying new designs that evolve rapidly, using constrained ...

Marvell

Principal, IC Digital Design Engineer

Irvine, CA · On-site

$146K/yr

Implement and drive the full ASIC frontend design flow , including lint, CDC/RDC, synthesis, timing ... Engineering, Computer Engineering, or related field ; PhD is a plus. Preferred / Plus Skills

Broadcom, Inc.

ASIC Design Verification Engineer

Irvine, CA · On-site

$129K - $207K/yr

We are looking for highly skilled and efficient Constrained Random Design Verification engineers that want to verify new designs that can evolve rapidly at every generation in a very dynamic market ...

Silvus Technologies

FPGA Design Engineer

Irvine, CA · On-site

$132K - $181K/yr

FPGA Design Engineers are responsible for the efficient implementation of novel signal processing ... Experience with communication systems on FPGA or ASIC designs. WORKING CONDITIONS AND PHYSICAL ...

Marvell Technology, Inc.

Digital Design Engineer

Irvine, CA · On-site

$146K/yr

Responsible for design, verification, implementation (ASIC) for high-performance, physical layer ... Develop ASIC specification, architecture, and micro-architecture of major functional blocks in ...

Marvell

Digital Design Engineer

Irvine, CA · On-site

$146K/yr

Responsible for design, verification, implementation (ASIC) for high-performance, physical layer ... Develop ASIC specification, architecture, and micro-architecture of major functional blocks in ...

OMNIVISION

Analog Design Engineer

Irvine, CA · On-site

$125K - $135K/yr

... asic_pixel array, column-amplifier, comparator, ramp generator, ASRAM and XDEC by using Cadence ... Collaborate with Digital Engineer to define and design the analog to digital interface; Collaborate ...

OMNIVISION

Analog Design Engineer

Irvine, CA

... asic_pixel array, column-amplifier, comparator, ramp generator, ASRAM and XDEC by using Cadence ... Collaborate with Digital Engineer to define and design the analog to digital interface; Collaborate ...

OMNIVISION

Analog Design Engineer

Irvine, CA

$125K - $135K/yr

... asic_pixel array, column-amplifier, comparator, ramp generator, ASRAM and XDEC by using Cadence ... Collaborate with Digital Engineer to define and design the analog to digital interface; Collaborate ...

OmniVision Technologies

Analog Design Engineer

Irvine, CA · On-site

$125K - $135K/yr

... asic_pixel array, column-amplifier, comparator, ramp generator, ASRAM and XDEC by using Cadence ... Collaborate with Digital Engineer to define and design the analog to digital interface; Collaborate ...

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All JobsGoogle Asic Design Engineer JobsGoogle Asic Design Engineer Jobs in Riverside, CA

Google Asic Design Engineer information

See Riverside, CA salary details

$98.1K

$156.7K

$210.7K

How much do google asic design engineer jobs pay per year?

As of Aug 20, 2026, the average yearly pay for google asic design engineer in Riverside, CA is $156,694.00, according to ZipRecruiter salary data. Most workers in this role earn between $137,200.00 and $187,800.00 per year, depending on experience, location, and employer.

What does a Google ASIC Design Engineer do?

A Google ASIC Design Engineer is responsible for designing and developing custom integrated circuits, known as Application-Specific Integrated Circuits (ASICs), that power Google's data centers, cloud infrastructure, and consumer devices. Their work involves collaborating with cross-functional teams to define requirements, create architecture, perform logic and physical design, and validate the silicon before production. They use advanced design tools and methodologies to ensure high performance, low power consumption, and reliability. Ultimately, their contributions help improve the efficiency and capabilities of Google's hardware products.

How does a Google ASIC Design Engineer typically collaborate with cross-functional teams during the chip development process?

As a Google ASIC Design Engineer, you will work closely with teams such as architecture, verification, software, and hardware validation to ensure successful chip delivery. Collaboration often involves regular meetings to align on design specifications, resolve integration issues, and discuss performance optimization. Effective communication is essential, as you’ll need to translate requirements from system architects into detailed hardware designs and provide feedback to verification and validation teams. This cross-functional interaction fosters a dynamic work environment and helps ensure the final product meets Google's rigorous standards.

What are the key skills and qualifications needed to thrive as a Google ASIC Design Engineer, and why are they important?

To thrive as a Google ASIC Design Engineer, you need a strong background in electrical engineering, digital logic design, and experience with ASIC development, typically backed by a relevant degree. Familiarity with hardware description languages (such as Verilog or VHDL), EDA tools (like Synopsys or Cadence), and an understanding of SoC architectures are essential, and related certifications can be valuable. Strong problem-solving skills, attention to detail, and effective teamwork and communication abilities help set candidates apart. These skills are crucial for designing reliable, high-performance ASICs that meet Google's specifications and project timelines.

What is the difference between Google Asic Design Engineer vs Google FPGA Design Engineer?

AspectGoogle Asic Design EngineerGoogle FPGA Design Engineer
Required CredentialsBachelor's/Master's in Electrical Engineering or Computer Engineering; experience in ASIC designBachelor's/Master's in Electrical Engineering or Computer Engineering; FPGA design experience
Work EnvironmentDesigning custom silicon chips for Google productsDeveloping and testing FPGA prototypes for hardware acceleration
Employer & Industry UsagePrimarily in semiconductor and hardware design teams at GoogleHardware prototyping and acceleration teams at Google

The main difference between a Google Asic Design Engineer and a Google FPGA Design Engineer lies in their focus: ASIC engineers design custom chips for optimized performance, while FPGA engineers develop flexible hardware prototypes using field-programmable gate arrays. Both roles require strong electrical engineering skills but serve different stages of hardware development.

Are Google ASIC Design Engineers in demand?

ASIC Design Engineers at Google are in high demand due to the growing need for specialized hardware acceleration and efficient chip designs in data centers and AI applications. Skills in digital design, verification, and hardware description languages like Verilog or VHDL are highly valued, and the role often requires experience with EDA tools and FPGA prototyping. The demand is expected to remain strong as companies continue to develop custom chips for performance and energy efficiency.

How much does a Google ASIC Design Engineer make?

A Google ASIC Design Engineer typically earns a base salary ranging from $120,000 to $200,000 annually, with total compensation often including bonuses and stock options. Compensation varies based on experience, location, and level within the company, and the role requires expertise in hardware design, verification, and EDA tools.

What is the salary of Google ASIC Design Engineer in Google?

The salary for a Google ASIC Design Engineer typically ranges from $120,000 to $200,000 annually, depending on experience, location, and level within the company. Compensation may also include bonuses, stock options, and benefits, reflecting industry standards for specialized hardware design roles at major tech companies.

What are popular job titles related to Google Asic Design Engineer jobs in Riverside, CA?

For Google Asic Design Engineer jobs in Riverside, CA, the most frequently searched job titles are:

What job categories do people searching Google Asic Design Engineer jobs in Riverside, CA look for?

The top searched job categories for Google Asic Design Engineer jobs in Riverside, CA are:

What cities near Riverside, CA are hiring for Google Asic Design Engineer jobs?

Cities near Riverside, CA with the most Google Asic Design Engineer job openings:

Google Asic Design Engineer jobs near you
Infographic showing various Google Asic Design Engineer job openings in Riverside, CA as of August 2026, with employment types broken down into 84% Full Time, 8% Part Time, and 8% Contract. Highlights an 100% In-person job distribution, with an average salary of $156,694 per year, or $75.3 per hour.

Principal Digital Design Engineer

GreenWave Radios

Irvine, CA • On-site

$146K/yr

Full-time

Re-posted 5 days ago

Job description

InnoPhase Inc., DBA GreenWave Radios™, is at the forefront of innovation in Open RAN digital radios. Our cutting-edge solutions, powered by the Hermes64 RF SoC, are designed to enhance network energy efficiency while dramatically reducing operational expenses, with purpose-built silicon that is the heart of ORAN-based active antenna arrays.
Headquartered in San Diego, California, GreenWave Radios™ has established itself as a pioneer in delivering power-efficient digital-to-RF solutions. The company is supported by a talented team of over 100 engineers spread across four global R&D facilities. With an extensive portfolio of more than 120 global patents, GreenWave Radios™ continues to push the boundaries of radio technology and innovation.
To learn more about GreenWave Radios™ and hear what our employees have to say, visit the GreenWave™ certification profile at GreatPlacetoWork.com or explore our Home - GreenWave Radios website.
About the Role
We're looking for an experienced Principal Engineer/Manager to lead a small, high-impact team building next-generation cellular infrastructure radio Front Haul Gateway (FHGW) solutions in both FPGA and ASIC. You'll own everything from architecture through production-defining features, authoring device specifications, and driving the design flow for high-performance programmable logic with embedded Linux-based wireless communications software. This is a senior technical leadership and management role with direct influence on our market-leading cellular infrastructure products, working hands-on alongside experts across design, verification, firmware, and system engineering.
What You'll Do
  • Lead and mentor a small team of FPGA/ASIC design engineers, including resource planning, project scheduling, and technical mentoring/oversight
  • Own solution architecture end-to-end-taking marketing requirements and translating to product specifications through production-quality programmable logic design, verification and hardware validation
  • Drive architecture / micro-architecture definition, CPU/bus/memory subsystem design, IP integration, and physical implementation for complex SoC designs
  • Collaborate with system engineering on Radio product specifications, ensuring alignment across the company
  • Partner with IP, design verification, firmware, software, and production teams to close design issues and meet program milestones
  • Refine development methodologies and enforce design quality standards across the team, including simulation, linting, clock-domain crossing checks, and formal verification
  • Collaborate with embedded Linux-based wireless communications software team that complements the FPGA/ASIC logic layer

What You Bring
  • 20+ years of experience in FPGA and SoC development and mass production, including a proven track record in a technical leadership and management role
  • MS or PhD in Electrical Engineering or equivalent
  • Deep expertise in Verilog and SystemVerilog, and front-end tooling (simulation, linting, CDC, formal verification)
  • Hands-on experience with packet processing designs including buffering, routing, transposing, combining, framing/de-framing packet based formats (e.g. Ethernet, O-RAN/eCPRI, etc)
  • Hands-on experience with AMBA AXI/AHB/APB bus protocol specification and implementation
  • Proven ability to define constraints, run synthesis and static timing analysis, and own a complete front-to-back AMD (Xilinx Vivado) FPGA implementation flow
  • Working knowledge of DFT/DFM, SCAN ATPG, BIST, and fault coverage analysis
  • Proficiency in SystemVerilog and other advanced design verification methodologies
  • Comfort with scripting and programming languages including C/C++, Perl, Tcl, and Python
  • Strong communication and presentation skills; ability to drive results under aggressive schedules across cross-functional teams
Nice to Have
  • Experience developing cellular infrastructure radio products, particularly 10/25Gbps Ethernet eCPRI connectivity to the DU and interface to RF ASICs.
  • Familiarity with O-RAN FS7.2x specifications or eCPRI/CPRI front haul protocols
  • Understanding of Array based radios including AAU and mMIMO
  • Exposure to AI-assisted EDA tools for synthesis, timing analysis, or verification (e.g., AI-driven placement/routing assistants, ML-based timing closure prediction, AI-guided power analysis)
  • Experience using Claude Code or similar AI coding assistants to accelerate design scripting, documentation, or code review - familiarity with agentic AI tools for engineering workflows is a genuine differentiator
  • Familiarity with LLM-assisted RTL or HDL generation tools (e.g., Copilot for hardware, or general-purpose LLMs prompted for Verilog/SystemVerilog generation and review)
  • Comfort using AI tools for verification productivity - assertion generation, coverage analysis, or ML-based bug prediction to speed up simulation closure
  • Experience applying AI to technical documentation workflows - LLM-assisted datasheet parsing, specification drafting, or design review summarization
  • General comfort adopting AI-augmented workflows to boost design productivity
Compensation and Benefits
At InnoPhase, dba GreenWave Radios, our total rewards package includes both a competitive base salary and pre-IPO stock options. The anticipated base salary range for this position is $190,000 to $225,000 annually. Actual compensation will be determined based on several factors, including market conditions, interview performance, skills, qualifications, experience, education, and geographic location. In addition to base pay, employees are eligible for a comprehensive benefits package. For detailed information on our benefits programs, please visit our website.

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