Debug SoC Design Engineer
$175K - $308K/yr
... integrated engineering team spanning RF/Analog architecture and design, Systems/PHY/MAC ... This is a highly visible role, where you will be at the center of the ASIC debug efforts ...
$175K - $308K/yr
... integrated engineering team spanning RF/Analog architecture and design, Systems/PHY/MAC ... This is a highly visible role, where you will be at the center of the ASIC debug efforts ...
$175K - $308K/yr
... integrated engineering team spanning RF/Analog architecture and design, Systems/PHY/MAC ... This is a highly visible role, where you will be at the center of the ASIC debug efforts ...
$175K - $308K/yr
... integrated engineering team spanning RF/Analog architecture and design, Systems/PHY/MAC ... This is a highly visible role, where you will be at the center of the ASIC debug efforts ...
$175K - $308K/yr
... integrated engineering team spanning RF/Analog architecture and design, Systems/PHY/MAC ... This is a highly visible role, where you will be at the center of the ASIC debug efforts ...
$175K - $308K/yr
... integrated engineering team spanning RF/Analog architecture and design, Systems/PHY/MAC ... This is a highly visible role, where you will be at the center of the ASIC debug efforts ...
$175K - $308K/yr
... integrated engineering team spanning RF/Analog architecture and design, Systems/PHY/MAC ... This is a highly visible role, where you will be at the center of the ASIC debug efforts ...
$132K - $181K/yr
FPGA Design Engineers are responsible for the efficient implementation of novel signal processing ... Experience with communication systems on FPGA or ASIC designs. WORKING CONDITIONS AND PHYSICAL ...
$132K - $181K/yr
FPGA Design Engineers are responsible for the efficient implementation of novel signal processing ... Experience with communication systems on FPGA or ASIC designs. WORKING CONDITIONS AND PHYSICAL ...
Responsible for design, verification, implementation (ASIC) for high-performance, physical layer ... Develop ASIC specification, architecture, and micro-architecture of major functional blocks in ...
Responsible for design, verification, implementation (ASIC) for high-performance, physical layer ... Develop ASIC specification, architecture, and micro-architecture of major functional blocks in ...
Irvine, CA · On-site
$132K - $182K/yr
FPGA Design Engineers are responsible for the efficient implementation of novel signal processing ... Experience with communication systems on FPGA or ASIC designs. THE OFFER * 140-200k base ...
Irvine, CA · On-site
$132K - $182K/yr
FPGA Design Engineers are responsible for the efficient implementation of novel signal processing ... Experience with communication systems on FPGA or ASIC designs. THE OFFER * 140-200k base ...
$108K - $192K/yr
ASIC Design Engineering: Deep understanding of ASIC design, including logic circuits, memory, PLL/Analog, Place and route, STA, DFT, DFM, etc. * The Debug Specialist: You know your way around scan ...
$108K - $192K/yr
ASIC Design Engineering: Deep understanding of ASIC design, including logic circuits, memory, PLL/Analog, Place and route, STA, DFT, DFM, etc. * The Debug Specialist: You know your way around scan ...
Irvine, CA · On-site
$146K/yr
Responsible for design, verification, implementation (ASIC) for high-performance, physical layer ... Develop ASIC specification, architecture, and micro-architecture of major functional blocks in ...
Irvine, CA · On-site
$146K/yr
Responsible for design, verification, implementation (ASIC) for high-performance, physical layer ... Develop ASIC specification, architecture, and micro-architecture of major functional blocks in ...
Irvine, CA · On-site
$125K - $135K/yr
... asic_pixel array, column-amplifier, comparator, ramp generator, ASRAM and XDEC by using Cadence ... Collaborate with Digital Engineer to define and design the analog to digital interface; Collaborate ...
Irvine, CA · On-site
$125K - $135K/yr
... asic_pixel array, column-amplifier, comparator, ramp generator, ASRAM and XDEC by using Cadence ... Collaborate with Digital Engineer to define and design the analog to digital interface; Collaborate ...
Irvine, CA · On-site
$108K - $192K/yr
ASIC Design Engineering: Deep understanding of ASIC design, including logic circuits, memory, PLL/Analog, Place and route, STA, DFT, DFM, etc. * The Debug Specialist: You know your way around scan ...
Irvine, CA · On-site
$108K - $192K/yr
ASIC Design Engineering: Deep understanding of ASIC design, including logic circuits, memory, PLL/Analog, Place and route, STA, DFT, DFM, etc. * The Debug Specialist: You know your way around scan ...
... asic_pixel array, column-amplifier, comparator, ramp generator, ASRAM and XDEC by using Cadence ... Collaborate with Digital Engineer to define and design the analog to digital interface; Collaborate ...
Quick apply
... asic_pixel array, column-amplifier, comparator, ramp generator, ASRAM and XDEC by using Cadence ... Collaborate with Digital Engineer to define and design the analog to digital interface; Collaborate ...
Irvine, CA · On-site
$125K - $135K/yr
... asic_pixel array, column-amplifier, comparator, ramp generator, ASRAM and XDEC by using Cadence ... Collaborate with Digital Engineer to define and design the analog to digital interface; Collaborate ...
Irvine, CA · On-site
$125K - $135K/yr
... asic_pixel array, column-amplifier, comparator, ramp generator, ASRAM and XDEC by using Cadence ... Collaborate with Digital Engineer to define and design the analog to digital interface; Collaborate ...
$125K - $135K/yr
... asic_pixel array, column-amplifier, comparator, ramp generator, ASRAM and XDEC by using Cadence ... Collaborate with Digital Engineer to define and design the analog to digital interface; Collaborate ...
$125K - $135K/yr
... asic_pixel array, column-amplifier, comparator, ramp generator, ASRAM and XDEC by using Cadence ... Collaborate with Digital Engineer to define and design the analog to digital interface; Collaborate ...
Irvine, CA · On-site
$146K - $150K/yr
Your Team, Your Impact Built on decades of expertise and execution, Marvell's custom Processor/ASIC ... In this unique role, you'll have the opportunity to work on both the physical design and ...
Irvine, CA · On-site
$146K - $150K/yr
Your Team, Your Impact Built on decades of expertise and execution, Marvell's custom Processor/ASIC ... In this unique role, you'll have the opportunity to work on both the physical design and ...
Irvine, CA · On-site
... engineering team spanning RF/Analog architecture, and design, Systems/PHY/MAC architecture and design, VLSI/RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW ...
Irvine, CA · On-site
... engineering team spanning RF/Analog architecture, and design, Systems/PHY/MAC architecture and design, VLSI/RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW ...
$145K - $175K/yr
RFIC DESIGN ENGINEER (RFIC ENGINEERING) At SpaceX we're leveraging our experience in building ... Work with system architects, modem/DSP and ASIC engineers to partition functions between hardware ...
$145K - $175K/yr
RFIC DESIGN ENGINEER (RFIC ENGINEERING) At SpaceX we're leveraging our experience in building ... Work with system architects, modem/DSP and ASIC engineers to partition functions between hardware ...
Irvine, CA · On-site
$100K - $140K/yr
FPGA Design Engineers are responsible for the efficient implementation of novel signal processing ... Experience with communication systems on FPGA or ASIC designs. WORKING CONDITIONS AND PHYSICAL ...
Irvine, CA · On-site
$100K - $140K/yr
FPGA Design Engineers are responsible for the efficient implementation of novel signal processing ... Experience with communication systems on FPGA or ASIC designs. WORKING CONDITIONS AND PHYSICAL ...
Irvine, CA · On-site
... engineering team spanning RF/Analog architecture, and design, Systems/PHY/MAC architecture and design, VLSI/RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW ...
Irvine, CA · On-site
... engineering team spanning RF/Analog architecture, and design, Systems/PHY/MAC architecture and design, VLSI/RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW ...
Irvine, CA · On-site
... engineering team spanning RF/Analog architecture, and design, Systems/PHY/MAC architecture and design, VLSI/RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW ...
Irvine, CA · On-site
... engineering team spanning RF/Analog architecture, and design, Systems/PHY/MAC architecture and design, VLSI/RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW ...
Irvine, CA · On-site
$132K - $181K/yr
FPGA Design Engineers are responsible for the efficient implementation of novel signal processing ... Experience with wireless communication systems on FPGA or ASIC designs. WORKING CONDITIONS ...
Irvine, CA · On-site
$132K - $181K/yr
FPGA Design Engineers are responsible for the efficient implementation of novel signal processing ... Experience with wireless communication systems on FPGA or ASIC designs. WORKING CONDITIONS ...
$98.1K - $108.3K
16% of jobs
$108.3K - $118.6K
3% of jobs
$118.6K - $128.8K
4% of jobs
$131.8K is the 25th percentile. Wages below this are outliers.
$128.8K - $139K
6% of jobs
The median wage is $145.5K / yr.
$139K - $149.3K
33% of jobs
$149.3K - $159.5K
3% of jobs
$159.5K - $169.8K
2% of jobs
$176.5K is the 75th percentile. Wages above this are outliers.
$169.8K - $180K
12% of jobs
$180K - $190.3K
5% of jobs
$190.3K - $200.5K
4% of jobs
$200.5K - $210.7K
12% of jobs
$98.1K
$156.7K
$210.7K
| Aspect | Google Asic Design Engineer | Google FPGA Design Engineer |
|---|---|---|
| Required Credentials | Bachelor's/Master's in Electrical Engineering or Computer Engineering; experience in ASIC design | Bachelor's/Master's in Electrical Engineering or Computer Engineering; FPGA design experience |
| Work Environment | Designing custom silicon chips for Google products | Developing and testing FPGA prototypes for hardware acceleration |
| Employer & Industry Usage | Primarily in semiconductor and hardware design teams at Google | Hardware prototyping and acceleration teams at Google |
The main difference between a Google Asic Design Engineer and a Google FPGA Design Engineer lies in their focus: ASIC engineers design custom chips for optimized performance, while FPGA engineers develop flexible hardware prototypes using field-programmable gate arrays. Both roles require strong electrical engineering skills but serve different stages of hardware development.

$175K - $308K/yr
Full-time
Medical, Dental, Retirement
Re-posted 18 days ago
8.1
Based on 670 frontline employees who took The Breakroom Quiz
5th of 30 rated technology retailers
Sourced by ZipRecruiter
Imagine what you could do here! At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, intelligent people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same real passion for innovation that goes into our products also applies to our practices strengthening our dedication to leave the world better than we found it.
Computer and electronic product manufacturing
10,000+ Employees
Cupertino, CA, US
1976