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Google Asic Design Engineer Jobs in Riverside, CA

... integrated engineering team spanning RF/Analog architecture and design, Systems/PHY/MAC ... This is a highly visible role, where you will be at the center of the ASIC debug efforts ...

... integrated engineering team spanning RF/Analog architecture and design, Systems/PHY/MAC ... This is a highly visible role, where you will be at the center of the ASIC debug efforts ...

... integrated engineering team spanning RF/Analog architecture and design, Systems/PHY/MAC ... This is a highly visible role, where you will be at the center of the ASIC debug efforts ...

FPGA Design Engineer

Irvine, CA

$132K - $181K/yr

FPGA Design Engineers are responsible for the efficient implementation of novel signal processing ... Experience with communication systems on FPGA or ASIC designs. WORKING CONDITIONS AND PHYSICAL ...

Responsible for design, verification, implementation (ASIC) for high-performance, physical layer ... Develop ASIC specification, architecture, and micro-architecture of major functional blocks in ...

Digital Design Engineer

Irvine, CA · On-site

$146K/yr

Responsible for design, verification, implementation (ASIC) for high-performance, physical layer ... Develop ASIC specification, architecture, and micro-architecture of major functional blocks in ...

Analog Design Engineer

Irvine, CA · On-site

$125K - $135K/yr

... asic_pixel array, column-amplifier, comparator, ramp generator, ASRAM and XDEC by using Cadence ... Collaborate with Digital Engineer to define and design the analog to digital interface; Collaborate ...

... asic_pixel array, column-amplifier, comparator, ramp generator, ASRAM and XDEC by using Cadence ... Collaborate with Digital Engineer to define and design the analog to digital interface; Collaborate ...

Analog Design Engineer

Irvine, CA · On-site

$125K - $135K/yr

... asic_pixel array, column-amplifier, comparator, ramp generator, ASRAM and XDEC by using Cadence ... Collaborate with Digital Engineer to define and design the analog to digital interface; Collaborate ...

... asic_pixel array, column-amplifier, comparator, ramp generator, ASRAM and XDEC by using Cadence ... Collaborate with Digital Engineer to define and design the analog to digital interface; Collaborate ...

Staff Physical Design Engineer

Irvine, CA · On-site

$146K - $150K/yr

Your Team, Your Impact Built on decades of expertise and execution, Marvell's custom Processor/ASIC ... In this unique role, you'll have the opportunity to work on both the physical design and ...

... engineering team spanning RF/Analog architecture, and design, Systems/PHY/MAC architecture and design, VLSI/RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW ...

FPGA Design Engineer

Irvine, CA · On-site

$100K - $140K/yr

FPGA Design Engineers are responsible for the efficient implementation of novel signal processing ... Experience with communication systems on FPGA or ASIC designs. WORKING CONDITIONS AND PHYSICAL ...

... engineering team spanning RF/Analog architecture, and design, Systems/PHY/MAC architecture and design, VLSI/RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW ...

... engineering team spanning RF/Analog architecture, and design, Systems/PHY/MAC architecture and design, VLSI/RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW ...

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Google Asic Design Engineer information

See Riverside, CA salary details

$98.1K

$156.7K

$210.7K

How much do google asic design engineer jobs pay per year?

As of Jul 14, 2026, the average yearly pay for google asic design engineer in Riverside, CA is $156,694.00, according to ZipRecruiter salary data. Most workers in this role earn between $137,200.00 and $187,800.00 per year, depending on experience, location, and employer.

What is the difference between Google Asic Design Engineer vs Google FPGA Design Engineer?

AspectGoogle Asic Design EngineerGoogle FPGA Design Engineer
Required CredentialsBachelor's/Master's in Electrical Engineering or Computer Engineering; experience in ASIC designBachelor's/Master's in Electrical Engineering or Computer Engineering; FPGA design experience
Work EnvironmentDesigning custom silicon chips for Google productsDeveloping and testing FPGA prototypes for hardware acceleration
Employer & Industry UsagePrimarily in semiconductor and hardware design teams at GoogleHardware prototyping and acceleration teams at Google

The main difference between a Google Asic Design Engineer and a Google FPGA Design Engineer lies in their focus: ASIC engineers design custom chips for optimized performance, while FPGA engineers develop flexible hardware prototypes using field-programmable gate arrays. Both roles require strong electrical engineering skills but serve different stages of hardware development.

How does a Google ASIC Design Engineer typically collaborate with cross-functional teams during the chip development process?

As a Google ASIC Design Engineer, you will work closely with teams such as architecture, verification, software, and hardware validation to ensure successful chip delivery. Collaboration often involves regular meetings to align on design specifications, resolve integration issues, and discuss performance optimization. Effective communication is essential, as you’ll need to translate requirements from system architects into detailed hardware designs and provide feedback to verification and validation teams. This cross-functional interaction fosters a dynamic work environment and helps ensure the final product meets Google's rigorous standards.

What does a Google ASIC Design Engineer do?

A Google ASIC Design Engineer is responsible for designing and developing custom integrated circuits, known as Application-Specific Integrated Circuits (ASICs), that power Google's data centers, cloud infrastructure, and consumer devices. Their work involves collaborating with cross-functional teams to define requirements, create architecture, perform logic and physical design, and validate the silicon before production. They use advanced design tools and methodologies to ensure high performance, low power consumption, and reliability. Ultimately, their contributions help improve the efficiency and capabilities of Google's hardware products.

What are the key skills and qualifications needed to thrive as a Google ASIC Design Engineer, and why are they important?

To thrive as a Google ASIC Design Engineer, you need a strong background in electrical engineering, digital logic design, and experience with ASIC development, typically backed by a relevant degree. Familiarity with hardware description languages (such as Verilog or VHDL), EDA tools (like Synopsys or Cadence), and an understanding of SoC architectures are essential, and related certifications can be valuable. Strong problem-solving skills, attention to detail, and effective teamwork and communication abilities help set candidates apart. These skills are crucial for designing reliable, high-performance ASICs that meet Google's specifications and project timelines.
What are popular job titles related to Google Asic Design Engineer jobs in Riverside, CA? For Google Asic Design Engineer jobs in Riverside, CA, the most frequently searched job titles are:
What job categories do people searching Google Asic Design Engineer jobs in Riverside, CA look for? The top searched job categories for Google Asic Design Engineer jobs in Riverside, CA are:
What cities near Riverside, CA are hiring for Google Asic Design Engineer jobs? Cities near Riverside, CA with the most Google Asic Design Engineer job openings:
Infographic showing various Google Asic Design Engineer job openings in Riverside, CA as of July 2026, with employment types broken down into 84% Full Time, 8% Part Time, and 8% Contract. Highlights an 100% In-person job distribution, with an average salary of $156,694 per year, or $75.3 per hour.
Debug SoC Design Engineer

Debug SoC Design Engineer

Apple

Irvine, CA

$175K - $308K/yr

Full-time

Medical, Dental, Retirement

Re-posted 18 days ago


Apple rating

8.1

Company rating: 8.1 out of 10

Based on 670 frontline employees who took The Breakroom Quiz

5th of 30 rated technology retailers


Job description

Come and join Apple’s growing wireless silicon development team. Our wireless SoC organization is responsible for all aspects of wireless silicon development, emphasizing highly energy-efficient design and new technologies that transform the user experience at the product level. All of this is driven by a world-class vertically integrated engineering team spanning RF/Analog architecture and design, Systems/PHY/MAC architecture and design, VLSI/RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW engineering. If you enjoy a fast-paced and challenging environment, collaborate with people across different functional areas, and thrive during crisis times, we encourage you to apply.
Description
In this role you will work on a small team designing CPU-based subsystems for high performance, low power wireless SoCs. You will work closely with SoC architects and IP developers to define debug features that meet the power, performance, and area goals.
You will own the design for the debug and trace hub. You will collaborate with other designers to ensure their subsystems implement the necessary debug features. You will guide validation engineers in the use of such features to diagnose issues. This is a highly visible role, where you will be at the center of the ASIC debug efforts, collaborating with all fields, with a critical impact in getting leading-edge products launched to delight millions of customers.","responsibilities":"RTL ownership of debug and trace hub - development, assessment, and refinement of RTL design to target power, performance, area and timing goals.
Micro-architecture development and specification - Work with a cross-functional team of silicon and software experts to explore and define architectural debug features, develop micro-architectural details, and arrive at a detailed specification.
Verification - support the verification team in test bench development and simulation/emulation for functional verification of debug features.
Performance/power correlation - assist performance/power teams to diagnose suspected bottlenecks or overconsumption.
Validation - Aid in debug of silicon issues at SoC level by employing the necessary debug features
Collaboration with multi-disciplinary groups to make sure designs are delivered on time and with the highest quality by incorporating proper checks at every stage of the design process.
Preferred Qualifications
Knowledge and understanding of microprocessor debug such as CoreSight and other debug techniques.
Shown experience writing micro-architecture specifications and converting them to design.
Experience with AXI/AHB bus fabric and processor sub-systems.
Understanding of UPF and low-power design & implementation techniques.
Self-starter and willingness to learn.
Minimum Qualifications
BS with 10+ years relevant experience.
Familiarity with the ASIC design flow.
Knowledge of digital design, SoC architecture, and HDL languages like Verilog.
Familiarity with design methodologies and industry standard EDA tools.
Pay & Benefits
At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $175,000 and $308,500, and your base pay will depend on your skills, qualifications, experience, and location.
Apple employees also have the opportunity to become an Apple shareholder through participation in Apple's discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple's Employee Stock Purchase Plan. You'll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses - including tuition. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation. Learn more about Apple Benefits
Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.

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About Apple

Sourced by ZipRecruiter

Imagine what you could do here! At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, intelligent people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same real passion for innovation that goes into our products also applies to our practices strengthening our dedication to leave the world better than we found it.

Industry

Computer and electronic product manufacturing

Company size

10,000+ Employees

Headquarters location

Cupertino, CA, US

Year founded

1976