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Google Asic Design Engineer Jobs in Riverside, CA

Apple

Debug SoC Design Engineer

Irvine, CA · On-site

$146K - $178K/yr

Familiarity with the ASIC design flow. Knowledge of digital design, SoC architecture, and HDL languages like Verilog. Familiarity with design methodologies and industry standard EDA tools. Preferred ...

Apple

Debug SoC Design Engineer

Irvine, CA · On-site

$146K - $178K/yr

... integrated engineering team spanning RF/Analog architecture and design, Systems/PHY/MAC ... This is a highly visible role, where you will be at the center of the ASIC debug efforts ...

Broadcom

ASIC Design Verification Engineer

Irvine, CA

$129K - $207K/yr

We are looking for highly skilled and efficient Constrained Random Design Verification engineers that want to verify new designs that can evolve rapidly at every generation in a very dynamic market ...

RED

FPGA/ASIC Engineer

Foothill Ranch, CA · On-site

$160K/yr

Responsibilities ASIC/FPGA Design * Oversees definition, design, verification, and documentation ... S. degree or higher in computer science, engineer, or mathematics * Location: Orange County, CA ...

Broadcom, Inc.

ASIC Design Verification Engineer

Irvine, CA · On-site

$129K - $207K/yr

We are looking for highly skilled and efficient Constrained Random Design Verification engineers that want to verify new designs that can evolve rapidly at every generation in a very dynamic market ...

Apple

Debug SoC Design Engineer

Irvine, CA

$122K - $214K/yr

... integrated engineering team spanning RF/Analog architecture and design, Systems/PHY/MAC ... This is a highly visible role, where you will be at the center of the ASIC debug efforts ...

Apple

Debug SoC Design Engineer

Irvine, CA

$175K - $308K/yr

... integrated engineering team spanning RF/Analog architecture and design, Systems/PHY/MAC ... This is a highly visible role, where you will be at the center of the ASIC debug efforts ...

Apple

Debug SoC Design Engineer

Irvine, CA

$122K - $214K/yr

... integrated engineering team spanning RF/Analog architecture and design, Systems/PHY/MAC ... This is a highly visible role, where you will be at the center of the ASIC debug efforts ...

Apple

Debug SoC Design Engineer

Irvine, CA

$122K - $214K/yr

... integrated engineering team spanning RF/Analog architecture and design, Systems/PHY/MAC ... This is a highly visible role, where you will be at the center of the ASIC debug efforts ...

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All JobsGoogle Asic Design Engineer JobsGoogle Asic Design Engineer Jobs in Riverside, CA

Google Asic Design Engineer information

See Riverside, CA salary details

$98.1K

$156.7K

$210.7K

How much do google asic design engineer jobs pay per year?

As of Jul 13, 2026, the average yearly pay for google asic design engineer in Riverside, CA is $156,694.00, according to ZipRecruiter salary data. Most workers in this role earn between $137,200.00 and $187,800.00 per year, depending on experience, location, and employer.

What is the difference between Google Asic Design Engineer vs Google FPGA Design Engineer?

AspectGoogle Asic Design EngineerGoogle FPGA Design Engineer
Required CredentialsBachelor's/Master's in Electrical Engineering or Computer Engineering; experience in ASIC designBachelor's/Master's in Electrical Engineering or Computer Engineering; FPGA design experience
Work EnvironmentDesigning custom silicon chips for Google productsDeveloping and testing FPGA prototypes for hardware acceleration
Employer & Industry UsagePrimarily in semiconductor and hardware design teams at GoogleHardware prototyping and acceleration teams at Google

The main difference between a Google Asic Design Engineer and a Google FPGA Design Engineer lies in their focus: ASIC engineers design custom chips for optimized performance, while FPGA engineers develop flexible hardware prototypes using field-programmable gate arrays. Both roles require strong electrical engineering skills but serve different stages of hardware development.

How does a Google ASIC Design Engineer typically collaborate with cross-functional teams during the chip development process?

As a Google ASIC Design Engineer, you will work closely with teams such as architecture, verification, software, and hardware validation to ensure successful chip delivery. Collaboration often involves regular meetings to align on design specifications, resolve integration issues, and discuss performance optimization. Effective communication is essential, as you’ll need to translate requirements from system architects into detailed hardware designs and provide feedback to verification and validation teams. This cross-functional interaction fosters a dynamic work environment and helps ensure the final product meets Google's rigorous standards.

What does a Google ASIC Design Engineer do?

A Google ASIC Design Engineer is responsible for designing and developing custom integrated circuits, known as Application-Specific Integrated Circuits (ASICs), that power Google's data centers, cloud infrastructure, and consumer devices. Their work involves collaborating with cross-functional teams to define requirements, create architecture, perform logic and physical design, and validate the silicon before production. They use advanced design tools and methodologies to ensure high performance, low power consumption, and reliability. Ultimately, their contributions help improve the efficiency and capabilities of Google's hardware products.

What are the key skills and qualifications needed to thrive as a Google ASIC Design Engineer, and why are they important?

To thrive as a Google ASIC Design Engineer, you need a strong background in electrical engineering, digital logic design, and experience with ASIC development, typically backed by a relevant degree. Familiarity with hardware description languages (such as Verilog or VHDL), EDA tools (like Synopsys or Cadence), and an understanding of SoC architectures are essential, and related certifications can be valuable. Strong problem-solving skills, attention to detail, and effective teamwork and communication abilities help set candidates apart. These skills are crucial for designing reliable, high-performance ASICs that meet Google's specifications and project timelines.
What are popular job titles related to Google Asic Design Engineer jobs in Riverside, CA? For Google Asic Design Engineer jobs in Riverside, CA, the most frequently searched job titles are:
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Google Asic Design Engineer jobs near you
Infographic showing various Google Asic Design Engineer job openings in Riverside, CA as of July 2026, with employment types broken down into 84% Full Time, 8% Part Time, and 8% Contract. Highlights an 100% In-person job distribution, with an average salary of $156,694 per year, or $75.3 per hour.
Physical Design Engineer II (Silicon Engineering)

Physical Design Engineer II (Silicon Engineering)

SpaceX

Irvine, CA

$145K - $195K/yr

Other

Medical, Dental, Vision, Life, Retirement, PTO

Posted 29 days ago

SpaceX rating

8.8

Company rating: 8.8 out of 10

Based on 146 frontline employees who took The Breakroom Quiz

7th of 61 rated aerospace companies

Job description

PHYSICAL DESIGN ENGINEER II (SILICON ENGINEERING)

At SpaceX we're leveraging our experience in building rockets and spacecraft to deploy Starlink, the world's most advanced broadband internet system. Starlink is the world's largest satellite constellation and is providing fast, reliable internet to millions of users worldwide. We design, build, test, and operate all parts of the system - thousands of satellites, consumer receivers that allow users to connect within minutes of unboxing, and the software that brings it all together. We've only begun to scratch the surface of Starlink's potential global impact and are looking for best-in-class engineers to help maximize Starlink's utility for communities and businesses around the globe. 

We are seeking a motivated, proactive, and intellectually curious engineer who will work alongside world-class cross-disciplinary teams (systems, firmware, architecture, design, validation, product engineering, ASIC implementation). In this role, you will be developing cutting-edge next-generation ASICs for deployment in space and ground infrastructures around the globe. These chips are enabling connectivity in places it has previously not been available, affordable or reliable. Your efforts will help deliver cutting-edge solutions that will expand the performance and capabilities of the Starlink network.

RESPONSIBILITIES:

  • Perform partition synthesis and physical implementation steps (e.g. synthesis, floorplanning, power/ground grid generation, place and route, timing, noise, physical verification, electromigration, voltage drop, logic equivalency and other signoff checks)
  • Develop/improve physical design methodologies and automation scripts for various implementation steps
  • Closely collaborate with the ASIC design team to drive architectural feasibility studies, develop timing, power and area design targets, and explore RTL/design tradeoffs
  • Resolve design/timing/congestion and flow issues, identify potential solutions and drive execution
  • Run, debug, and fix signoff closure issues in static timing analysis (STA), noise, logic equivalency, physical verification, electromigration and voltage drop

BASIC QUALIFICATIONS:

  • Bachelor's degree in electrical engineering, computer engineering or computer science
  • 3+ years of professional experience working on RTL2GDSII physical design and/or physical design flow development

PREFERRED SKILLS AND EXPERIENCE:

  • Experience with industry standard EDA tools including understanding of their capabilities and underlying algorithms
  • Knowledge of deep sub-micron FinFET and CMOS solid state physics
  • Understanding of CMOS digital design principles, basic standard cells their functionality, standard cell libraries
  • Understanding of CMOS power dissipation in deep submicron processes leakage/dynamic
  • Familiar with CMOS analog circuit and physical design
  • Basic knowledge of DFT/Scan/MBIST/LBIST and understanding of their impact on physical design flows
  • Good scripting skills (csh/bash, Perl, Python, TCL, Makefile etc.)
  • Self-driven individual with a can-do attitude, willing to learn, and an ability to work in a dynamic group environment

ADDITIONAL REQUIREMENTS:

  • Ability to work extended hours and weekends as needed to meet critical project milestones

COMPENSATION AND BENEFITS:

Pay range:    
Physical Design Engineer/Level II: $145,000.00 - $195,000.00/per year    
Your actual level and base salary will be determined on a case-by-case basis and may vary based on the following considerations: job-related knowledge and skills, education, and experience.

Base salary is just one part of your total rewards package at SpaceX. You may also be eligible for long-term incentives, in the form of company stock, stock options, or long-term cash awards, as well as potential discretionary bonuses and the ability to purchase additional stock at a discount through an Employee Stock Purchase Plan. You will also receive access to comprehensive medical, vision, and dental coverage, access to a 401(k) retirement plan, short & long-term disability insurance, life insurance, paid parental leave, and various other discounts and perks. You may also accrue 3 weeks of paid vacation & will be eligible for 10 or more paid holidays per year. Exempt employees are eligible for 5 days of sick leave per year.

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