1

Google Asic Design Engineer Jobs in New York (NOW HIRING)

ASIC Engineer

New York, NY

$181K/yr

About the Position We are looking to hire an experienced ASIC Engineer to help us design, test and deploy advanced hardware designs. As part of our Ultra Low Latency team, you'll have the opportunity ...

ASIC Engineer

New York, NY · On-site

$181K/yr

About the Position We are looking to hire an experienced ASIC Engineer to help us design, test and deploy advanced hardware designs. As part of our Ultra Low Latency team, you'll have the opportunity ...

ASIC Physical Design Engineer

New York, NY · On-site

$148K - $153K/yr

About the Position We are looking to hire an ASIC Physical Design Engineer to help us design, test, and deploy advanced hardware. As part of our Ultra Low Latency team, you'll have the opportunity to ...

ASIC Physical Design Engineer

New York, NY

$148K - $153K/yr

About the Position We are looking to hire an ASIC Physical Design Engineer to help us design, test, and deploy advanced hardware. As part of our Ultra Low Latency team, you'll have the opportunity to ...

About the Position We are looking to hire engineers with experience in both software and hardware design to help us build our FPGA or ASIC-based applications. We're big believers in the ability of ...

Hardware Engineer, RTL

New York, NY · On-site

$200K - $400K/yr

This work sits at the intersection of classical ASIC design, novel computing architectures, and a ... This is a role for an engineer who collaborates effectively across teams, including architecture ...

Systems Engineering Lead

Clifton, NJ · On-site

$127K - $236K/yr

The SME works across systems engineering, ASIC design, RF design, hardware, software, packaging, test, manufacturing, and program management teams to translate operational needs into achievable ...

We expect interns to build hardware applications from concept to a working design; your projects ... Comfortable with a software programming language * Experienced with a Hardware Description (or ...

Hardware Engineer, RTL

Manhattan, NY · On-site

$120 - $160/hr

The Role As an RTL Design Engineer at Normal, you will design and verify the digital logic at the ... This work sits at the intersection of classical ASIC design, novel computing architectures, and a ...

next page

Showing results 1-20

Google Asic Design Engineer information

See New York salary details

$102.8K

$164.3K

$221K

How much do google asic design engineer jobs pay per year?

As of Aug 29, 2026, the average yearly pay for google asic design engineer in New York is $164,319.00, according to ZipRecruiter salary data. Most workers in this role earn between $143,900.00 and $196,900.00 per year, depending on experience, location, and employer.

What does a Google ASIC Design Engineer do?

A Google ASIC Design Engineer is responsible for designing and developing custom integrated circuits, known as Application-Specific Integrated Circuits (ASICs), that power Google's data centers, cloud infrastructure, and consumer devices. Their work involves collaborating with cross-functional teams to define requirements, create architecture, perform logic and physical design, and validate the silicon before production. They use advanced design tools and methodologies to ensure high performance, low power consumption, and reliability. Ultimately, their contributions help improve the efficiency and capabilities of Google's hardware products.

How does a Google ASIC Design Engineer typically collaborate with cross-functional teams during the chip development process?

As a Google ASIC Design Engineer, you will work closely with teams such as architecture, verification, software, and hardware validation to ensure successful chip delivery. Collaboration often involves regular meetings to align on design specifications, resolve integration issues, and discuss performance optimization. Effective communication is essential, as you’ll need to translate requirements from system architects into detailed hardware designs and provide feedback to verification and validation teams. This cross-functional interaction fosters a dynamic work environment and helps ensure the final product meets Google's rigorous standards.

What are the key skills and qualifications needed to thrive as a Google ASIC Design Engineer, and why are they important?

To thrive as a Google ASIC Design Engineer, you need a strong background in electrical engineering, digital logic design, and experience with ASIC development, typically backed by a relevant degree. Familiarity with hardware description languages (such as Verilog or VHDL), EDA tools (like Synopsys or Cadence), and an understanding of SoC architectures are essential, and related certifications can be valuable. Strong problem-solving skills, attention to detail, and effective teamwork and communication abilities help set candidates apart. These skills are crucial for designing reliable, high-performance ASICs that meet Google's specifications and project timelines.

What is the difference between Google Asic Design Engineer vs Google FPGA Design Engineer?

AspectGoogle Asic Design EngineerGoogle FPGA Design Engineer
Required CredentialsBachelor's/Master's in Electrical Engineering or Computer Engineering; experience in ASIC designBachelor's/Master's in Electrical Engineering or Computer Engineering; FPGA design experience
Work EnvironmentDesigning custom silicon chips for Google productsDeveloping and testing FPGA prototypes for hardware acceleration
Employer & Industry UsagePrimarily in semiconductor and hardware design teams at GoogleHardware prototyping and acceleration teams at Google

The main difference between a Google Asic Design Engineer and a Google FPGA Design Engineer lies in their focus: ASIC engineers design custom chips for optimized performance, while FPGA engineers develop flexible hardware prototypes using field-programmable gate arrays. Both roles require strong electrical engineering skills but serve different stages of hardware development.

Are Google ASIC Design Engineers in demand?

ASIC Design Engineers at Google are in high demand due to the growing need for specialized hardware acceleration and efficient chip designs in data centers and AI applications. Skills in digital design, verification, and hardware description languages like Verilog or VHDL are highly valued, and the role often requires experience with EDA tools and FPGA prototyping. The demand is expected to remain strong as companies continue to develop custom chips for performance and energy efficiency.

How much does a Google ASIC Design Engineer make?

A Google ASIC Design Engineer typically earns a base salary ranging from $120,000 to $200,000 annually, with total compensation often including bonuses and stock options. Compensation varies based on experience, location, and level within the company, and the role requires expertise in hardware design, verification, and EDA tools.

What is the salary of Google ASIC Design Engineer in Google?

The salary for a Google ASIC Design Engineer typically ranges from $120,000 to $200,000 annually, depending on experience, location, and level within the company. Compensation may also include bonuses, stock options, and benefits, reflecting industry standards for specialized hardware design roles at major tech companies.

What are popular job titles related to Google Asic Design Engineer jobs in New York?

For Google Asic Design Engineer jobs in New York, the most frequently searched job titles are:

What job categories do people searching Google Asic Design Engineer jobs in New York look for?

The top searched job categories for Google Asic Design Engineer jobs in New York are:

What cities in New York are hiring for Google Asic Design Engineer jobs?

Cities in New York with the most Google Asic Design Engineer job openings:

Infographic showing various Google Asic Design Engineer job openings in New York as of August 2026, with employment types broken down into 5% As Needed, 76% Full Time, and 19% Contract. Highlights an 91% In-person, and 9% Remote job distribution, with an average salary of $164,319 per year, or $79 per hour.

Senior Digital ASIC Design Engineer

Manhattan, NY • On-site

Brookhaven National Laboratory
Scientific Research and Development Services • 1 - 5K employees

$115 - $145/hr

Other

Posted 24 days ago


Job description

## Senior Digital ASIC Design EngineerApplylocations: Upton, NYtime type: Full timeposted on: Posted 2 Days Agojob requisition id: JR102590The mission of the Instrumentation Division is to develop state-of-the-art instrumentation required for experimental research programs at Brookhaven Lab and to maintain the expertise and facilities in specialized high technology areas essential for this work. Development of facilities is motivated by present Brookhaven research programs and anticipated future directions of research. Our work has a significant impact on programs throughout the world that rely on state-of-the-art radiation detectors, readout electronics, data acquisition systems, and scientific instrumentation.We seek a motivated Senior Digital ASIC Design Engineer to join our team as a senior digital designer for developing advanced readout ASICs and system-on-chip architectures for scientific instrumentation. The successful candidate will contribute to microelectronics for the Electron-Ion Collider (EIC), including ePIC detector systems, while also supporting ASICs for other programs in high-energy physics, nuclear physics, photon sciences, quantum information science, and related instrumentation efforts at BNL and with external partners.In this role, you will lead the architecture, RTL design, implementation, and integration of digital blocks and subsystems for mixed-signal ASICs used in detector readout, trigger and timing distribution, data concentration, control, calibration, and high-speed data transmission. You will collaborate closely with analog and mixed-signal designers, verification engineers, physical design engineers, firmware developers, detector scientists, and other technical team members in the ASIC group, the Instrumentation Division, and the broader scientific community. We look for candidates with strong digital ASIC design expertise, particularly in low-power, radiation-aware, timing-critical, and data-intensive systems for scientific applications.Our science and engineering challenges are complex and unique! We are engaged in the development of ASICs for particle detectors, high-resolution X- and gamma-ray spectrometers, high-rate photon counters and imagers, cryogenic and radiation-tolerant instrumentation, and other specialized systems for high-energy physics, nuclear physics, photon sciences, quantum information science, and related scientific programs. Our ASICs may operate in extreme environments, must meet stringent power, timing, noise, and radiation requirements, and must integrate reliably with sensors, FPGAs, data acquisition systems, and laboratory test infrastructure. The applications of these ASICs extend beyond BNL to national and international user facilities: your work will have the potential to shape the instruments used for scientific discovery and engineering advancements across the globe!**Essential Duties and Responsibilities:*** Take a lead role in the architecture, microarchitecture, RTL design, and integration of digital ASICs and digital subsystems for scientific instruments, including EIC detector readout and related programs* Develop design specifications based on detector, data acquisition, timing, power, radiation, and system integration requirements in conjunction with scientists, engineers, and project stakeholders* Design and implement synthesizable RTL in SystemVerilog/Verilog for blocks such as data formatting, sparsification, buffering, trigger and timing interfaces, configuration and control, calibration logic, digital signal processing, and high-speed link interfaces* Develop and maintain reusable digital IP, register maps, bus interfaces, clock and reset architectures, memory interfaces, finite-state machines, FIFOs, error detection/correction logic, and monitoring features suitable for ASIC integration* Carry out or contribute to synthesis, static timing analysis, clock-domain crossing analysis, reset-domain crossing analysis, power estimation, linting, design-for-test insertion, and timing-driven physical implementation in Cadence, Synopsys, Siemens, or similar CAD/EDA environments* Work closely with physical design and analog/mixed-signal teams to ensure successful floorplanning, partitioning, timing closure, power integrity, signal integrity, and mixed-signal integration* Coordinate with verification engineers to define verification plans, develop self-checking test benches, review functional coverage, debug simulations, and close design issues before tapeout* Support FPGA prototyping, laboratory evaluation, test-board development, bring-up, characterization, and integration of ASICs with sensors, firmware, and data acquisition systems* Lead technical documentation, design reviews, interface control documents, and contributions to new project initiatives and proposals making use of emerging microelectronics technologies**Required Knowledge, Skills, and Abilities:*** Bachelor's degree in electrical engineering, computer engineering, applied physics, or a closely related field of study* Minimum seven (7) years of progressively responsible related work experience in digital ASIC design* Demonstrated experience developing synthesizable RTL in SystemVerilog and/or Verilog for complex ASICs or system-on-chip designs* Familiarity with ASIC design processes and flows, CAD/EDA tools for ASIC design, and their interoperability across design, verification, synthesis, timing, and physical implementation* Experience with digital architecture, clocking and reset strategies, timing constraints, CDC/RDC methodology, low-power design considerations, and debugging of large digital systems* Ability to work effectively with group members in a multi-user, process-design-kit-managed, version-controlled design environment and to step up to technical and schedule challenges* Excellent written and oral communication skills, including the ability to document designs, participate in reviews, and work with multidisciplinary scientific and engineering teams**Preferred Knowledge, Skills, and Abilities:*** Master's or Ph.D. in electrical engineering, computer engineering, applied physics, or a closely related field of study* Experience with readout integrated circuits for radiation detectors, including detector timing, triggering, sparsified data readout, high-speed data transmission, calibration, and slow-control functions* Experience with ASICs for particle physics, nuclear physics, photon sciences, cryogenic instrumentation, space or radiation environments, or other scientific applications* Experience with digital implementation tools and flows such as synthesis, static timing analysis, formal equivalence checking, lint, CDC/RDC analysis, power analysis, DFT/scan, and automated place and route* Familiarity with common on-chip bus and control interfaces such as AXI, AHB, APB, Wishbone, I2C, SPI, JTAG, and custom detector-readout protocols* Experience with scripting and automation using Tcl, Python, Perl, Make, shell scripting, or similar tools in an EDA environment* Knowledge of radiation-tolerant design techniques, single-event-effect mitigation, triple modular redundancy, error detection/correction, and design approaches for low-power or cryogenic operation* Experience working with firmware, FPGA prototyping, board-level test systems, and laboratory characterization of ASICs**Additional Information:*** **This is a fully onsite position located at Brookhaven National Laboratory in Upton, NY.**Brookhaven National Laboratory is committed to providing fair, equitable and competitive compensation. The full salary range for this position is $115000 - $145000 / year. Salary offers will be commensurate with the final candidate’s qualification, education and experience and considered with the internal peer group. **Brookhaven National Laboratory is committed to employee success and we believe that a comprehensive employee benefits program is an important and meaningful part of the compensation employees receive. Review more information at** **BNL | Benefits Program** Brookhaven National Laboratory requires all non-badged personnel including visitors to produce a REAL-ID or REAL-ID compliant documentation to access Brookhaven National Laboratory – view more information at www.bnl.gov/real-id. This is due to nationwide identification requirements for federal site access as required by the federal REAL ID Act. **Those not in possession of a REAL ID-compliant document will not be permitted to access the site which includes access to the Laboratory for interviews**. As a U.S. Department of Energy laboratory, Brookhaven National Laboratory requires employees to obtain and maintain a DOE Uncleared Personal Identity Verification (UPIV) credential in accordance with Homeland Security Presidential Directive 12 (HSPD-12) requirements. The credentialing process is completed as part of onboarding and enables access to DOE facilities and information systems. As a condition of employment, the selected candidate must be able to obtain and maintain a UPIV credential. These requirements are established under DOE Order 206.2 Chg. 2, *Identity, Credential, and Access Management (ICAM-* Identity, Credential, and Access Management (ICAM)*)*, and DOE Order 473.1A- Physical Protection Program- Physical Protection Program. **About Us**Brookhaven National Laboratory (www.bnl.gov) delivers discovery science and transformative technology to power and secure the nation’s future. Brookhaven Lab is a multidisciplinary laboratory with seven Nobel Prize-winning discoveries, 37 R&D 100 Awards, and more than 70 years of pioneering research. The Lab is primarily supported by the U.S. Department of Energy’s (DOE) Office of Science. Brookhaven Science Associates (BSA) operates and manages the Laboratory for DOE. BSA is a partnership between Battelle and The Research Foundation for the State University of New York on behalf of Stony Brook University. BSA salutes our veterans and active military members with careers that leverage the skills and unique experience they gained while serving our country, learn more at BNL | Opportunities for Veterans at Brookhaven National Laboratory. **Equal Opportunity/Affirmative Action Employer**Guided by our core values of integrity, responsibility, innovation, respect, and teamwork, Brookhaven Science Associates is an Equal Employment Opportunity Employer-Vets/Disabled. We are committed to fostering a respectful and collaborative environment that fuels scientific discovery. We consider all qualified applicants without regard to any characteristic protected by law. All qualified individuals are encouraged to apply. We ensure that individuals with disabilities are provided reasonable accommodation to participate in the job application or interview process, to perform essential job functions, and to receive other benefits and privileges of employment. Please contact us to request accommodation. \*VEVRAA Federal Contractor BSA employees are subject to restrictions related to participation in Foreign Government Talent Recruitment Programs, as defined and detailed in United States Department of Energy Order 486.1A. You will be asked to disclose any such participation at the time of hire for review by Brookhaven. The full text of the Order may be found at: https://www.directives.doe.gov/directives-documents/400-series/0486.1-BOrder-a/@@images/file #J-18808-Ljbffr