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Asic Design Verification Jobs (NOW HIRING)

Your Impact As an ASIC Design Verification Engineer, you will play a critical role in developing Cisco's revolutionary data center solutions. You'll architect and develop DV infrastructure, create ...

Meta is hiring ASIC Design Verification Engineer within the Infrastructure organization. We are looking for individuals with experience in Design Verification to build IP and System On Chip (SoC) for ...

Meta is hiring ASIC Design Verification Engineer within the Infrastructure organization. We are looking for individuals with experience in Design Verification to build IP and System On Chip (SoC) for ...

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Asic Design Verification information

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$88K

$156.1K

$207K

How much do asic design verification jobs pay per year?

As of Aug 23, 2026, the average yearly pay for asic design verification in the United States is $156,077.00, according to ZipRecruiter salary data. Most workers in this role earn between $136,000.00 and $175,500.00 per year, depending on experience, location, and employer.

What is ASIC Design Verification?

ASIC Design Verification is the process of ensuring that an Application-Specific Integrated Circuit (ASIC) design functions as intended before it is manufactured. This involves creating and running tests, simulations, and checks to detect and correct errors in the design. Verification engineers use specialized tools and methodologies such as simulation, formal verification, and emulation to verify the logic and performance of the ASIC. Thorough verification helps prevent costly mistakes and ensures the final chip meets all specifications.

What are the key skills and qualifications needed to thrive as an ASIC Design Verification engineer?

To thrive as an ASIC Design Verification Engineer, you need a solid background in digital design concepts, verification methodologies, and a degree in electrical or computer engineering. Proficiency with hardware description languages like Verilog or VHDL, verification tools such as UVM/SystemVerilog, and simulation/debugging environments is essential. Strong analytical thinking, attention to detail, and effective communication skills help you identify design flaws and collaborate with cross-functional teams. These skills are critical to ensuring the reliability, efficiency, and functionality of complex integrated circuits before production.

What are some common challenges faced in ASIC Design Verification, and how can they be addressed?

One of the main challenges in ASIC Design Verification is dealing with increasing design complexity and ensuring that all functional requirements are thoroughly tested within tight project timelines. To address this, verification engineers often use advanced methodologies such as UVM (Universal Verification Methodology) and leverage automation tools for testbench creation and regression testing. Effective collaboration with design engineers is also essential to quickly resolve issues and ensure alignment between the design and verification teams. Maintaining good documentation and regularly updating test plans helps keep the verification process organized and efficient.
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What cities are hiring for Asic Design Verification jobs?

Cities with the most Asic Design Verification job openings:

What are the most commonly searched types of Asic Design Verification jobs?

The most popular types of Asic Design Verification jobs are:

What states have the most Asic Design Verification jobs?

States with the most job openings for Asic Design Verification jobs include:

Infographic showing various Asic Design Verification job openings in the United States as of August 2026, with employment types broken down into 89% Full Time, 7% Part Time, and 4% Contract. Highlights an 83% Physical, 5% Hybrid, and 12% Remote job distribution, with an average salary of $156,077 per year, or $75 per hour.

Principal ASIC Design Verification Engineer

ForwardEdge ASIC LLC

Saint Paul, MN • On-site

$200K - $220K/yr

Other

Medical, Retirement, PTO

Re-posted 2 days ago


Job description

Position Description: At ForwardEdge ASIC we specialize in best-in-class ASIC technology, 100% domestically traceable microelectronic solutions designed for performance in commercial, aerospace, defense, and security sectors. FEASIC operates a full-scale ASIC design shop with cross-disciplinary fluency between digital logic, analog/mixed-signal design, and physical layout, and sits at the intersection of advanced ASIC, FPGA, and microelectronics design. As a wholly owned subsidiary of Lockheed Martin, we combine the agility of a startup with the stability and scale of a Fortune 100 leader. We operate in a nimble, fast-paced environment of 80+ highly experienced and specialized engineers with over 25 years of ASIC/FPGA experience and more than 300 patents. We are looking for a Principal ASIC Design Verification Engineer to provide technical leadership across complex digital and mixed-signal verification programs. This role is ideal for a senior verification expert who enjoys owning verification strategy, building scalable environments, solving difficult debug problems, and mentoring high-performing engineering teams.Position SummaryAs a Principal ASIC Design Verification Engineer, you will lead verification planning and execution for complex ASIC, SoC, subsystem, and FPGA designs. You will define verification architecture, develop reusable methodologies, drive coverage closure, and ensure designs meet functional, performance, and quality requirements.You will work closely with architecture, RTL design, analog/mixed-signal, firmware, FPGA, emulation, and program teams to deliver high-quality silicon. In this role, you will serve as both a hands-on technical contributor and a verification leader, helping establish best practices and guiding other engineers through challenging verification efforts.Key Responsibilities• Lead verification strategy, planning, and execution for complex ASIC, SoC, subsystem, IP, and FPGA designs.• Define verification architecture, testbench structure, verification plans, coverage models, and signoff criteria.• Develop and maintain scalable verification environments using SystemVerilog, UVM, assertions, constrained-random testing, and directed testing.• Create and review verification plans, functional coverage models, scoreboards, monitors, checkers, sequences, and reusable verification components.• Drive verification closure using functional coverage, code coverage, assertion coverage, regression results, and bug metrics.• Lead debug of complex failures across RTL, testbench, firmware, gate-level simulation, emulation, and system-level environments.• Collaborate closely with architects, RTL designers, analog/mixed-signal engineers, firmware developers, and project leads to ensure complete and efficient verification.• Serve as the verification technical authority in customer architecture and signoff reviews.• Provide effort estimation and verification staffing input for proposals and new program pursuits.• Mentor junior and senior verification engineers through technical reviews, methodology guidance, and hands-on debug support.• Improve verification productivity through automation, scripting, reusable infrastructure, and methodology enhancements.• Evaluate and apply industry-standard tools and methodologies, including simulation, formal verification, emulation, FPGA prototyping, and verification management tools.• Support project planning by estimating verification scope, identifying risks, tracking progress, and communicating status to technical and program leadership.Qualifications• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related technical field.• Typically 12+ years of ASIC, SoC, or FPGA design verification experience, with demonstrated ownership of complex verification efforts.• Expert-level experience with SystemVerilog and UVM.• Strong background developing block-level, subsystem-level, or SoC-level verification environments.• Experience creating verification plans, coverage models, constrained-random tests, directed tests, assertions, and regression strategies.• Strong understanding of verification closure, including functional coverage, code coverage, assertion coverage, bug triage, and signoff methodology.• Hands-on debug experience with complex RTL and testbench issues.• Proficiency with scripting and automation using languages such as Python, Perl, Tcl, shell scripting, or Make.• Experience with industry-standard EDA simulation, debug, coverage, and verification management tools.• Strong technical leadership skills, including experience mentoring engineers and guiding verification execution.• Excellent written and verbal communication skills.• Ability to collaborate effectively across architecture, design, verification, analog, firmware, FPGA, and program teams.Preferred Qualifications• Experience with high-speed interfaces and protocols such as PCIe, CXL, DDR, LPDDR, Ethernet, USB, MIPI, AMBA, AXI, CHI, or UCIe.• Experience contributing to proposals, scoping, or technical pre-sales in a design-services context• Experience with formal verification, assertion-based verification, or property checking.• Experience with gate-level simulation, low-power verification, UPF/CPF, reset verification, or X-propagation analysis.• Experience with emulation, FPGA prototyping, hardware/software co-verification, or post-silicon bring-up support.• Familiarity with mixed-signal verification methodologies.• Experience working in customer-facing engineering environments or design services organizations.Why Join ForwardEdge ASIC?At ForwardEdge ASIC, you will work on challenging silicon programs with a highly experienced engineering team. You will have the opportunity to influence verification strategy, contribute to advanced ASIC development, and help deliver high-quality custom silicon solutions for leading-edge applications.What We Offer• Work-Life Balance: Flexible 9/80 work schedule with every other Friday off• Competitive Comp & Benefits: Healthcare and medical coverage options, 401(k) retirement benefits with company contribution, generous holidays and PTO• Incentives: Eligibility for short-term and long-term incentive programsJoin ForwardEdge ASIC and be part of a team that thrives on innovation and excellence in ASIC design. Together, we build the technology that enables a safer, more resilient world. $200,000.00 - $220,000.00 Annually