ASIC Engineer
New York, NY · On-site
$181K/yr
Have 4+ years practical experience in RTL design and verification * Experienced in ASIC design using either Synopsys or Cadence flows, including at least one of the following: * Front-end RTL design ...
New York, NY · On-site
$181K/yr
Have 4+ years practical experience in RTL design and verification * Experienced in ASIC design using either Synopsys or Cadence flows, including at least one of the following: * Front-end RTL design ...
New York, NY · On-site
$181K/yr
Have 4+ years practical experience in RTL design and verification * Experienced in ASIC design using either Synopsys or Cadence flows, including at least one of the following: * Front-end RTL design ...
New York, NY · On-site
$181K/yr
Have 4+ years practical experience in RTL design and verification * Experienced in ASIC design using either Synopsys or Cadence flows, including at least one of the following: * Front-end RTL design ...
New York, NY · On-site
$181K/yr
Have 4+ years practical experience in RTL design and verification * Experienced in ASIC design using either Synopsys or Cadence flows, including at least one of the following: * Front-end RTL design ...
Manhattan, NY · On-site
$115 - $145/hr
## Senior Digital ASIC Design EngineerApplylocations: Upton, NYtime type: Full timeposted on: Posted 2 ... You will collaborate closely with analog and mixed-signal designers, verification engineers ...
Manhattan, NY · On-site
$115 - $145/hr
## Senior Digital ASIC Design EngineerApplylocations: Upton, NYtime type: Full timeposted on: Posted 2 ... You will collaborate closely with analog and mixed-signal designers, verification engineers ...
New York, NY · On-site
$200K - $400K/yr
Thermodynamic ASIC Verification: Own design verification for Normal's internal silicon: testbench environments, assertions, and coverage from design documents through functional coverage and closure ...
New York, NY · On-site
$200K - $400K/yr
Thermodynamic ASIC Verification: Own design verification for Normal's internal silicon: testbench environments, assertions, and coverage from design documents through functional coverage and closure ...
New York, NY · On-site
$148K - $181K/yr
... ASIC technologies to drive low latency trading decisions on global markets. We build custom ... We are looking for Design Verification (DV) engineers who are passionate about writing testbenches ...
New York, NY · On-site
$148K - $181K/yr
... ASIC technologies to drive low latency trading decisions on global markets. We build custom ... We are looking for Design Verification (DV) engineers who are passionate about writing testbenches ...
Manhattan, NY · On-site
$120 - $170/hr
This work sits at the intersection of classical ASIC design, novel computing architectures, and a ... Verification : Work closely with the verification team to review verification plans, assist on ...
Manhattan, NY · On-site
$120 - $170/hr
This work sits at the intersection of classical ASIC design, novel computing architectures, and a ... Verification : Work closely with the verification team to review verification plans, assist on ...
New York, NY · On-site
$148K - $181K/yr
... ASIC technologies to drive low latency trading decisions on global markets. We build custom ... We are looking for Design Verification (DV) engineers who are passionate about writing testbenches ...
New York, NY · On-site
$148K - $181K/yr
... ASIC technologies to drive low latency trading decisions on global markets. We build custom ... We are looking for Design Verification (DV) engineers who are passionate about writing testbenches ...
Holmdel, NJ · On-site
$154K - $225K/yr
... Verification Test (DVT) Engineer to design and run automated testing of PIC devices, assist ... optical packaging, ASIC development, and the operations teams to deliver leading edge, high ...
Holmdel, NJ · On-site
$154K - $225K/yr
... Verification Test (DVT) Engineer to design and run automated testing of PIC devices, assist ... optical packaging, ASIC development, and the operations teams to deliver leading edge, high ...
... Verification Test (DVT) Engineer to design and run automated testing of PIC devices, assist ... optical packaging, ASIC development, and the operations teams to deliver leading edge, high ...
... Verification Test (DVT) Engineer to design and run automated testing of PIC devices, assist ... optical packaging, ASIC development, and the operations teams to deliver leading edge, high ...
Totowa, NJ · On-site
$97K - $164K/yr
Experience with FPGA/ASIC design and verification tools (Mentor Questa or Cadence) * Proven track record of executing to schedule, and driving tasks to closure. Candidates should also be comfortable ...
New
Totowa, NJ · On-site
$97K - $164K/yr
Experience with FPGA/ASIC design and verification tools (Mentor Questa or Cadence) * Proven track record of executing to schedule, and driving tasks to closure. Candidates should also be comfortable ...
New
Perform physical verification activities including DRC, LVS, ERC, and reliability checks in ... Strong experience in physical design for ASIC/SoC development, including successful implementation ...
Perform physical verification activities including DRC, LVS, ERC, and reliability checks in ... Strong experience in physical design for ASIC/SoC development, including successful implementation ...
NJ · On-site
The diagnostics Software is target to verify ASIC, FPGA, Board and system designs in Engineering as ... design verification and validation in engineering and manufacturing. • Work closely with HW ...
New
NJ · On-site
The diagnostics Software is target to verify ASIC, FPGA, Board and system designs in Engineering as ... design verification and validation in engineering and manufacturing. • Work closely with HW ...
New
Totowa, NJ · On-site
$130K - $221K/yr
Experience with FPGA/ASIC design and verification tools (Mentor Questa or Cadence) * Proven track record of managing and executing to schedules, and driving tasks to closure. Candidates should also ...
Totowa, NJ · On-site
$130K - $221K/yr
Experience with FPGA/ASIC design and verification tools (Mentor Questa or Cadence) * Proven track record of managing and executing to schedules, and driving tasks to closure. Candidates should also ...
Totowa, NJ · On-site
$130K - $221K/yr
Experience with FPGA/ASIC design and verification tools (Mentor Questa or Cadence) * Proven track record of managing and executing to schedules, and driving tasks to closure. Candidates should also ...
Totowa, NJ · On-site
$130K - $221K/yr
Experience with FPGA/ASIC design and verification tools (Mentor Questa or Cadence) * Proven track record of managing and executing to schedules, and driving tasks to closure. Candidates should also ...
Somerset, NJ · On-site
$143K - $147K/yr
Perform physical verification activities including DRC, LVS, ERC, and reliability checks in ... Strong experience in physical design for ASIC/SoC development, including successful implementation ...
Somerset, NJ · On-site
$143K - $147K/yr
Perform physical verification activities including DRC, LVS, ERC, and reliability checks in ... Strong experience in physical design for ASIC/SoC development, including successful implementation ...
New York, NY · On-site
$200K - $400K/yr
The Role As an RTL Design Engineer at Normal, you will design and verify the digital logic at the heart of Normal's thermodynamic hardware. This work sits at the intersection of classical ASIC design ...
New York, NY · On-site
$200K - $400K/yr
The Role As an RTL Design Engineer at Normal, you will design and verify the digital logic at the heart of Normal's thermodynamic hardware. This work sits at the intersection of classical ASIC design ...
New York, NY · On-site
$200K - $400K/yr
Sitting at the intersection of custom ASIC design and our hardware-algorithm co-designed systems ... Physical Signoff & Verification: Execute full chip/block physical signoff checks, including DRC ...
New York, NY · On-site
$200K - $400K/yr
Sitting at the intersection of custom ASIC design and our hardware-algorithm co-designed systems ... Physical Signoff & Verification: Execute full chip/block physical signoff checks, including DRC ...
New York, NY · On-site
$150K - $250K/yr
You will coordinate with our Software, Architecture, Design Verification (DV), Physical Design, System Design, and Data Center teams. The ideal candidate combines technical fluency in the ASIC ...
New York, NY · On-site
$150K - $250K/yr
You will coordinate with our Software, Architecture, Design Verification (DV), Physical Design, System Design, and Data Center teams. The ideal candidate combines technical fluency in the ASIC ...
Clifton, NJ · On-site
$127K - $236K/yr
Assess the impact of RF ASIC design decisions on overall system performance, integration risk, cost, and schedule. * Support verification, validation, and technical risk management across the full ...
Clifton, NJ · On-site
$127K - $236K/yr
Assess the impact of RF ASIC design decisions on overall system performance, integration risk, cost, and schedule. * Support verification, validation, and technical risk management across the full ...
Clifton, NJ · On-site
Assess the impact of RF ASIC design decisions on overall system performance, integration risk, cost, and schedule. * Support verification, validation, and technical risk management across the full ...
Clifton, NJ · On-site
Assess the impact of RF ASIC design decisions on overall system performance, integration risk, cost, and schedule. * Support verification, validation, and technical risk management across the full ...
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We are looking to hire an experienced ASIC Engineer to help us design, test and deploy advanced hardware designs. As part of our Ultra Low Latency team, you'll have the opportunity to collaborate with people in areas across the firm, including trading, networking and research infrastructure. We are looking for someone who can contribute to all of our projects and be happy to work on both FPGA-based and ASIC-based technologies.
We're big believers in the ability of tools to improve the productivity, reliability and day-to-day joy of hardware engineering. That's why we created Hardcaml, a hardware development toolchain embedded in OCaml. We don't expect you to know OCaml (we'll teach you here), but we are looking for hardware engineers who are excited about the advantages that better tools can bring, and are willing to try new things as a result.
About YouIf you're a recruiting agency and want to partner with us, please reach out to agency-partnerships@janestreet.com.
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Finance and insurance
1,001 - 5,000 Employees
New York, NY, US
2000