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Asic Architect Jobs (NOW HIRING)

ASIC Architect

Saratoga, CA ยท On-site

$210K - $275K/yr

Position Overview We are looking for a highly experienced ASIC Architect to contribute to the definition and implementation of Eridu's industry leading networking products. This is a unique ...

What You Can Expect The ASIC Architect serves as a senior technical leader within the company, guiding the evolution of capabilities across our leading-edge SoCs and driving innovation to sustain the ...

As an Analog ASIC Architect on the Touch Technology team, you will own the architecture of complex mixed-signal ASICs from concept through silicon, with the goal of enabling best-in-class touch ...

In this AI/ML ASIC Architecture position, you will develop AI Storage Solutions based advanced system architectures and AI/ML Accelerator ASIC architecture specifications for Sandisk's next ...

ASIC Architect

San Jose, CA ยท On-site

$200K - $265K/yr

ASIC design flow and physical design constraints * Publishing or presenting at architecture conferences (ISCA, MICRO, HPCA, etc.) * Hands-on experience with tapeout and silicon bring-up Benefits

In this AI/ML ASIC Architecture position, you will develop AI Storage Solutions based advanced system architectures and AI/ML Accelerator ASIC architecture specifications for Sandisk's next ...

ASIC Architect

San Jose, CA ยท On-site

$200K - $265K/yr

PhD in Computer Science, Electrical Engineering, Computer Engineering, or related field * 5+ years of experience in computer architecture, ASIC design, or related fields * Strong understanding of ...

AI/ML ASIC Architect

Milpitas, CA ยท On-site

$136K - $226K/yr

In this AI/ML ASIC Architecture position, you will develop AI Storage Solutions based advanced system architectures and AI/ML Accelerator ASIC architecture specifications for Sandisk's next ...

In this AI/ML ASIC Architecture position, you will develop AI Storage Solutions based advanced system architectures and AI/ML Accelerator ASIC architecture specifications for Sandisk's next ...

What You Can Expect The ASIC Architect serves as a senior technical leader within the company, guiding the evolution of capabilities across our leadingedge SoCs and driving innovation to sustain the ...

Description As an Analog ASIC Architect on the Touch Technology team, you will own the architecture of complex mixed-signal ASICs from concept through silicon, with the goal of enabling best-in-class ...

In this AI/ML ASIC Architecture position, you will develop AI Storage Solutions based advanced system architectures and AI/ML Accelerator ASIC architecture specifications for Sandisk's next ...

AI/ML ASIC Architect

Milpitas, CA ยท On-site

$194K - $322K/yr

In this AI/ML ASIC Architecture position, you will develop AI Storage Solutions based advanced system architectures and AI/ML Accelerator ASIC architecture specifications for Sandisk's next ...

Analog ASIC Architect

Austin, TX ยท On-site

$181K - $318K/yr

Description As an Analog ASIC Architect on the Touch Technology team, you will own the architecture of complex mixed-signal ASICs from concept through silicon, with the goal of enabling best-in-class ...

In this AI/ML ASIC Architecture position, you will develop AI Storage Solutions based advanced system architectures and AI/ML Accelerator ASIC architecture specifications for Sandisk's next ...

In this role, you will lead all phases of ASIC architecture definition and design of Tensordyne's next-generation family of processors for generative AI inference acceleration. This is an exciting ...

In this role, you will lead all phases of ASIC architecture definition and design of Tensordyne's next-generation family of processors for generative AI inference acceleration. This is an exciting ...

ASIC Architect

Sunnyvale, CA ยท On-site

$196K/yr

Our novel wafer-scale architecture provides the AI compute power of dozens of GPUs on a single chip, with the programming simplicity of a single device. This approach allows Cerebras to deliver ...

Translate high level architecture spec to micro-architecture feature requirements * Bring up new features in the performance/power model * Perform comprehensive PPA trade-offs for new architectural ...

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Asic Architect information

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$131K

$168.6K

$197K

How much do asic architect jobs pay per year?

As of Jun 9, 2026, the average yearly pay for asic architect in the United States is $168,571.00, according to ZipRecruiter salary data. Most workers in this role earn between $155,000.00 and $183,000.00 per year, depending on experience, location, and employer.

What are ASIC Architects?

ASIC Architects are specialized engineers who design and oversee the development of Application-Specific Integrated Circuits (ASICs). They are responsible for defining the architecture, functionality, and performance requirements of custom chips used in various electronic devices. ASIC Architects collaborate with hardware and software teams to ensure the chip meets the desired specifications, optimizes performance, and stays within power and cost constraints. Their expertise is essential in industries like telecommunications, automotive, and consumer electronics, where tailored hardware solutions are critical.

What are the key skills and qualifications needed to thrive as an ASIC Architect, and why are they important?

To thrive as an ASIC Architect, you need deep expertise in digital and analog circuit design, computer architecture, and semiconductor technology, typically supported by a degree in electrical engineering or a related field. Proficiency with hardware description languages (such as Verilog or VHDL), EDA tools (like Synopsys or Cadence), and familiarity with ASIC development flows is essential. Strong problem-solving, communication, and project management skills help you collaborate effectively and drive complex projects to completion. These skills ensure the successful design, verification, and delivery of advanced integrated circuits that meet performance, power, and cost requirements.

What is the difference between Asic Architect vs FPGA Designer?

AspectAsic ArchitectFPGA Designer
CredentialsBachelor's or Master's in Electrical Engineering, VLSI Design, or related fields; certifications like IEEE or industry-specific coursesBachelor's or Master's in Electrical Engineering, VLSI Design, or related fields; similar certifications
Work EnvironmentDesigning custom integrated circuits for manufacturing; often in semiconductor companies or design firmsDeveloping programmable logic designs for specific applications; used in prototyping and flexible hardware solutions
Industry UsagePrimarily in semiconductor manufacturing, consumer electronics, and high-performance computingIn telecommunications, aerospace, and prototyping sectors

While both roles involve VLSI design and hardware development, Asic Architects focus on designing custom chips for mass production, whereas FPGA Designers work on flexible, programmable hardware solutions. The roles share similar credentials and work environments but differ in application and end-use.

What are some common challenges faced by ASIC Architects during the design phase, and how are they typically addressed?

ASIC Architects often encounter challenges such as balancing performance, power consumption, and chip area within strict project timelines. They must also ensure design compliance with specifications while coordinating with verification, physical design, and software teams. Effective communication, early identification of design bottlenecks, and iterative simulation are crucial strategies for addressing these challenges. Collaboration and regular design reviews help ensure that potential issues are resolved early, reducing costly redesigns later in the project.
More about Asic Architect jobs
What cities are hiring for Asic Architect jobs? Cities with the most Asic Architect job openings:
What states have the most Asic Architect jobs? States with the most job openings for Asic Architect jobs include:
Infographic showing various Asic Architect job openings in the United States as of May 2026, with employment types broken down into 80% Full Time, and 20% Part Time. Highlights an 86% Physical, 9% Hybrid, and 5% Remote job distribution, with an average salary of $168,571 per year, or $81 per hour.

ASIC Architect

Eridu AI

Saratoga, CA โ€ข On-site

$210K - $275K/yr

Full-time

Posted 23 days ago


Job description

About Eridu
Eridu is a Silicon Valley-based hardware startup pioneering infrastructure solutions that accelerate AI data centers to deliver Faster AI. Today's AI performance is frequently limited by communication bottlenecks. Eridu introduces multiple industry-first innovations across silicon, packaging, software, and systems to deliver an order of magnitude improvement in performance and unlock greater GPU utilization to speed training job completion times and tokens-per-second for more profitable inference. We do this while simultaneously reducing capital and power costs and improving reliability.
The company's solutions and value proposition have been widely validated by leading hyperscalers.
Eridu has raised over $200M to date including its most recent, oversubscribed Series A round. The company is led by a veteran team of Silicon Valley executives who have delivered multiple billion dollar product lines and led multiple companies to billion dollar exits, including serial entrepreneur Drew Perkins, co-founder of Infinera (NASDAQ: INFN), Lightera (acq. by Ciena), Gainspeed (acq. by Nokia) and Mojo Vision (the world's leading micro-LED company). The company is in execution mode and has a world-class engineering team with decades of experience in state-of-the-art silicon, packaging, optics, software, and systems. Eridu is working with best-in-class supply chain partners including silicon, packaging and systems.
Visit our website eridu.ai to learn more.
Position Overview
We are looking for a highly experienced ASIC Architect to contribute to the definition and implementation of Eridu's industry leading networking products. This is a unique opportunity to help shape the future of AI Networking.
Responsibilities
  • Work closely with the CTO to translate high-level system requirements and customer use cases into detailed architecture and functional specifications.
  • Collaborate with chip and system microarchitects to align ASIC architecture with system-level goals for throughput, latency, and power efficiency.
  • Guide modeling and feasibility analysis of packet flow behavior through the switch datapath to validate architectural choices, including throughput, latency, power and area efficiencies.
  • Work closely with RTL, Verification, Physical Design and Firmware teams to ensure seamless design implementation and handoff.
  • Guide integration of internal and external IPs (e.g. MAC, PCIe, SerDes) into the broader architecture. Drive interface requirements.
  • Participate in design reviews, performance modeling, test and verification strategies and architectural trade-off analysis.
  • Contribute to post-silicon validation for performance and correctness. Investigate and resolve complex issues related to ASIC data path, working closely with cross-functional teams including hardware engineers, firmware developers, and system architects.

Qualifications
  • MSEE with 10+ years of experience, preferably in networking ASIC architecture and design.
  • Candidates with experience in related areas of computer and parallel processing architectures - in particular, complex memory crossbars, buffering schemes, scheduling algorithms and high-speed datapaths - are also highly desired.
  • A deep understanding of networking protocols (Ethernet, TCP/IP, UDP, VLAN, MPLS, RoCE, etc.) and their hardware implications, or a willingness to become expert.
  • Demonstrated expertise in microarchitecture definition, performance modeling, and trade-off analysis. Capability to develop Architecture behavioral models is highly desired.
  • Experience working across the ASIC development lifecycle, from concept through productization.
  • Experience in high-speed I/O integration (e.g., PCIe Gen5/Gen6, SerDes) and Software Control Plane interface architecture is highly desirable.
  • Understanding of physical design implications on packet processing and buffering architecture (e.g., timing, area, power).
  • Strong analytical and problem-solving abilities, with meticulous attention to detail in troubleshooting and debugging complex issues. Exceptional written and verbal communication skills, including the ability to document and present complex architectural concepts clearly.

Why Join Us?
At Eridu, you'll have the opportunity to shape the future of AI infrastructure, working with a world-class team on groundbreaking technology that pushes the boundaries of AI performance. Your contributions will directly impact the next generation of AI infrastructure solutions, transforming the performance of AI data centers.
The starting base salary for the selected candidate will be established based on their relevant skills, experience, qualifications, work location, market trends, and the compensation of employees in comparable roles.
Notice to Recruiting Agencies
Eridu does not accept unsolicited resumes or candidate profiles from staffing agencies or third-party recruiters. Any candidate submitted to Eridu without prior written authorization from our recruiting team will be considered unsolicited and will become the property of Eridu. Eridu reserves the right to pursue and hire such candidates without any obligation to pay fees. Recruiting agencies are expressly instructed not to contact hiring managers, employees, or executives regarding open positions.
The pay range for this role is:
210,000 - 275,000 USD per year (San Francisco, Bay Area)