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Contractual Asic Rtl Design Engineer Jobs (NOW HIRING)

Ericsson

ASIC RTL Design Engineer

Austin, TX · On-site

ASIC RTL Design Engineer Hybrid work schedule This is not a remote work opportunity Silicon That Connects the World This Is Where Your Work Becomes Reality Not prototype reality. Not lab reality.

Qualcomm

Processor ASIC RTL Design Engineer

San Diego, CA · On-site

$127.20K - $190.80K/yr

Engineering Group, Engineering Group > DSP Architecture and Design General Summary: A variety of ... This position involves in-depth understanding of the ASIC design flow from RTL to GDS2 and the ...

ServerLogic

Senior ASIC Design Engineer

Beaverton, OR · On-site

Sr/ ASIC Design Engineer (5+ Years of Experience) DESCRIPTION OF POSITION/DUTIES - * Architect a ... Run LINT and CDC checks on the RTL code and fix accordingly. * Assist with synthesis and FPGA ...

TetraMem Inc

ASIC RTL/SoC Design Engineer

San Jose, CA · On-site

$110K - $300K/yr

Lead RTL design, simulation, and verification efforts for TetraMem ASIC/SoC products, ensuring ... Play a mentorship role by guiding and coaching junior engineers, sharing expertise and best ...

TetraMem INC

ASIC RTL/SoC Design Engineer

Fremont, CA · On-site

Lead RTL design, simulation, and verification efforts for TetraMem ASIC/SoC products, ensuring ... Play a mentorship role by guiding and coaching junior engineers, sharing expertise and best ...

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Contractual Asic Rtl Design Engineer information

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$94K

$150.2K

$202K

How much do contractual asic rtl design engineer jobs pay per year?

As of May 30, 2026, the average yearly pay for contractual asic rtl design engineer in the United States is $150,195.00, according to ZipRecruiter salary data. Most workers in this role earn between $131,500.00 and $180,000.00 per year, depending on experience, location, and employer.

What is the difference between Contractual Asic Rtl Design Engineer vs Digital IC Design Engineer?

AspectContractual Asic Rtl Design EngineerDigital IC Design Engineer
CredentialsBachelor's/Master's in Electrical Engineering or Computer EngineeringBachelor's/Master's in Electrical Engineering or Computer Engineering
Work EnvironmentContract-based, project-specific, often in semiconductor or tech companiesFull-time or contract, working on digital integrated circuit design
Industry UsageCommon in semiconductor, electronics, and tech firms for ASIC developmentUsed across semiconductor, consumer electronics, and communication industries

Both roles require similar educational backgrounds and work in related environments, focusing on digital circuit design. The main difference is that Contractual Asic Rtl Design Engineers typically work on specific ASIC projects on a contractual basis, while Digital IC Design Engineers may have broader responsibilities in digital chip development, often in full-time roles.

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Contractual Asic Rtl Design Engineer jobs near you
Infographic showing various Contractual Asic Rtl Design Engineer job openings in the United States as of May 2026, with employment types broken down into 14% Internship, 14% Full Time, and 72% Contract. Highlights an 90% Physical, and 10% Hybrid job distribution, with an average salary of $150,195 per year, or $72.2 per hour.

Lead ASIC RTL Design Engineer

4 Staffing Corp - Client Jobs

San Francisco, CA • On-site, Remote

$170K - $250K/yr

Full-time

Posted 15 days ago

Job description

Lead ASIC RTL Design Engineer — Remote (U.S.) - No visa sponsorship

Role Summary
Our client, a leader in AI Compute is seeking a senior-level ASIC design engineer to drive the development of high-performance silicon components used in advanced compute platforms. This individual will take ownership of key IP blocks from early architectural definition through RTL delivery and signoff, working closely with cross-functional teams to meet aggressive performance, power, and area goals. The role combines hands-on design work with technical leadership and mentorship.

Core Responsibilities

Architecture & RTL Development

  • Define microarchitecture for complex subsystems and document design specifications
  • Implement high-quality, reusable RTL in System Verilog with clear interface definitions and design intent
  • Incorporate assertions and design-for-debug features within RTL

Design Ownership & Implementation

  • Lead front-end design activities including linting, clock/reset domain analysis, and synthesis readiness
  • Collaborate with physical design teams on floor planning, timing closure, and implementation tradeoffs
  • Take responsibility for achieving performance, power, and area (PPA) targets for assigned blocks

High-Speed Interfaces & Memory Systems

  • Design and integrate high-bandwidth interfaces and interconnects (e.g., AMBA-based protocols, coherent fabrics)
  • Work on memory subsystem integration, including external DRAM and high-throughput memory solutions
  • Coordinate with internal teams and third-party IP providers to ensure proper integration and functionality

Engineering Processes & Tooling

  • Establish and maintain RTL design standards, reusable components, and signoff criteria
  • Contribute to automation and workflow improvements using scripting and build systems (Python, Tcl, CI pipelines)

Collaboration & System Integration

  • Partner with verification teams on test planning, coverage goals, and model alignment
  • Work with architecture and performance engineering to validate design intent against system-level expectations
  • Support silicon bring-up, debugging, and downstream customer or system integration efforts

Technical Leadership

  • Mentor less experienced engineers and provide guidance on design best practices
  • Lead design reviews and help drive key technical decisions across teams
  • Advocate for scalable, efficient, and high-quality engineering solutions

Basic Qualifications

  • Bachelor's or Master's degree in Electrical or Computer Engineering (or similar field)
  • 8+ years of experience in ASIC or SoC RTL design for complex, high-speed devices
  • Demonstrated experience delivering designs from concept through RTL implementation and tape out readiness
  • Strong System Verilog expertise, including clocking strategies, reset design, and domain crossing considerations
  • Hands-on experience with front-end design tools and flows (linting, CDC analysis, synthesis, timing analysis, DFT)
  • Familiarity with multiple high-speed technologies such as memory interfaces, interconnect protocols, or compute data paths
  • Strong communication skills with the ability to lead technical discussions and document designs clearly

Preferred Experience

  • Exposure to AI/ML hardware or high-performance compute architectures
  • Knowledge of formal verification techniques and assertion-based design
  • Experience with power optimization methods (e.g., clock gating, power intent formats like UPF/CPF)
  • Familiarity working alongside verification environments (UVM, Python-based frameworks, or similar)
  • Understanding of modern processor subsystems, coherence models, or custom tool flows