Staff ASIC Design Engineer
$140K - $170K/yr
Your responsibility will be developing RTL for both ASIC and FPGA design environments. You will collaborate with highly qualified and experienced digital design engineers on the team. You will work ...
$140K - $170K/yr
Your responsibility will be developing RTL for both ASIC and FPGA design environments. You will collaborate with highly qualified and experienced digital design engineers on the team. You will work ...
$140K - $170K/yr
Your responsibility will be developing RTL for both ASIC and FPGA design environments. You will collaborate with highly qualified and experienced digital design engineers on the team. You will work ...
Saint Paul, MN · On-site
$200K - $220K/yr
... RTL) code using industry standard hardware description languages. • Writing test plans and ... ASIC Design Engineer. • Experience in Synthesis, linting, clock domain crossing tools • ...
Saint Paul, MN · On-site
$200K - $220K/yr
... RTL) code using industry standard hardware description languages. • Writing test plans and ... ASIC Design Engineer. • Experience in Synthesis, linting, clock domain crossing tools • ...
$200K - $220K/yr
You will work closely with architecture, RTL design, analog/mixed-signal, firmware, FPGA, emulation ... Engineering, or a related technical field. • Typically 12+ years of ASIC, SoC, or FPGA design ...
$200K - $220K/yr
You will work closely with architecture, RTL design, analog/mixed-signal, firmware, FPGA, emulation ... Engineering, or a related technical field. • Typically 12+ years of ASIC, SoC, or FPGA design ...
Saint Paul, MN · On-site
$115K - $135K/yr
... digital logic, RTL design concepts, and hardware description languages. • Exposure to ... engineering environments.Why Join ForwardEdge ASIC?At ForwardEdge ASIC, you will have the ...
Saint Paul, MN · On-site
$115K - $135K/yr
... digital logic, RTL design concepts, and hardware description languages. • Exposure to ... engineering environments.Why Join ForwardEdge ASIC?At ForwardEdge ASIC, you will have the ...
Saint Paul, MN · On-site
$130K - $170K/yr
You will work with architects, RTL designers, analog/mixed-signal engineers, firmware developers ... ASIC, SoC, FPGA, or IP design verification experience. • Strong hands-on experience with ...
Saint Paul, MN · On-site
$130K - $170K/yr
You will work with architects, RTL designers, analog/mixed-signal engineers, firmware developers ... ASIC, SoC, FPGA, or IP design verification experience. • Strong hands-on experience with ...
$206K - $410K/yr
RTL Design: Author, review, and maintain synthesizable RTL (SystemVerilog) for all soft IP control ... ASIC/digital design experience with at least one prior tape-out in a chip lead, design lead, or ...
$206K - $410K/yr
RTL Design: Author, review, and maintain synthesizable RTL (SystemVerilog) for all soft IP control ... ASIC/digital design experience with at least one prior tape-out in a chip lead, design lead, or ...
Minneapolis, MN · On-site
$206K - $410K/yr
RTL Design: Author, review, and maintain synthesizable RTL (SystemVerilog) for all soft IP control ... ASIC/digital design experience with at least one prior tape-out in a chip lead, design lead, or ...
Minneapolis, MN · On-site
$206K - $410K/yr
RTL Design: Author, review, and maintain synthesizable RTL (SystemVerilog) for all soft IP control ... ASIC/digital design experience with at least one prior tape-out in a chip lead, design lead, or ...
Minneapolis, MN · On-site
$130K - $150K/yr
Physical Design Engineer (ASIC) Location: Minneapolis, MN (Onsite) Duration: Fulltime/Permanent ... KEY RESPONSIBILITIES • Lead efforts to translate customer designs into ASIC technology (RTL to ...
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Minneapolis, MN · On-site
$130K - $150K/yr
Physical Design Engineer (ASIC) Location: Minneapolis, MN (Onsite) Duration: Fulltime/Permanent ... KEY RESPONSIBILITIES • Lead efforts to translate customer designs into ASIC technology (RTL to ...
Moundsview, MN · On-site
We have an integrated ASIC team enabling engineers to wear many hats from digital design ... RTL Coding : Write clean, synthesizable, and high-performance RTL using SystemVerilog and Verilog.
Moundsview, MN · On-site
We have an integrated ASIC team enabling engineers to wear many hats from digital design ... RTL Coding : Write clean, synthesizable, and high-performance RTL using SystemVerilog and Verilog.
Moundsview, MN · On-site
We have an integrated ASIC team enabling engineers to wear many hats from digital design ... RTL Coding : Write clean, synthesizable, and high-performance RTL using SystemVerilog and Verilog.
Moundsview, MN · On-site
We have an integrated ASIC team enabling engineers to wear many hats from digital design ... RTL Coding : Write clean, synthesizable, and high-performance RTL using SystemVerilog and Verilog.
Moundsview, MN · On-site
We have an integrated ASIC team enabling engineers to wear many hats from digital design ... RTL Coding : Write clean, synthesizable, and high-performance RTL using SystemVerilog and Verilog.
Moundsview, MN · On-site
We have an integrated ASIC team enabling engineers to wear many hats from digital design ... RTL Coding : Write clean, synthesizable, and high-performance RTL using SystemVerilog and Verilog.
Bloomington, MN · On-site
$75 - $81/hr
Responsible for definition, design, verification and documentation for ASIC (Application Specific Integrated Circuit) and/or FPGA (Field Programmable Gate Array) developments * Determines ...
Bloomington, MN · On-site
$75 - $81/hr
Responsible for definition, design, verification and documentation for ASIC (Application Specific Integrated Circuit) and/or FPGA (Field Programmable Gate Array) developments * Determines ...
$75 - $81/hr
Responsible for definition, design, verification and documentation for ASIC (Application Specific Integrated Circuit) and/or FPGA (Field Programmable Gate Array) developments * Determines ...
$75 - $81/hr
Responsible for definition, design, verification and documentation for ASIC (Application Specific Integrated Circuit) and/or FPGA (Field Programmable Gate Array) developments * Determines ...
Saint Paul, MN · On-site
$80.81 - $85.81/hr
ASIC/FPGA Engineer Bloomington, MN Pay Estimated: $80.81 - $85.81/Hour U.S. Citizenship is required by Federal Law We are hiring a Mid-Level ASIC/FPGA Design Engineer in Bloomington, MN, to support ...
Saint Paul, MN · On-site
$80.81 - $85.81/hr
ASIC/FPGA Engineer Bloomington, MN Pay Estimated: $80.81 - $85.81/Hour U.S. Citizenship is required by Federal Law We are hiring a Mid-Level ASIC/FPGA Design Engineer in Bloomington, MN, to support ...
Bloomington, MN · On-site
$80.81 - $85.81/hr
ASIC/FPGA Engineer Bloomington, MN Pay Estimated: $80.81 - $85.81/Hour U.S. Citizenship is required by Federal Law We are hiring a Mid-Level ASIC/FPGA Design Engineer in Bloomington, MN, to support ...
Bloomington, MN · On-site
$80.81 - $85.81/hr
ASIC/FPGA Engineer Bloomington, MN Pay Estimated: $80.81 - $85.81/Hour U.S. Citizenship is required by Federal Law We are hiring a Mid-Level ASIC/FPGA Design Engineer in Bloomington, MN, to support ...
Senior ASIC Design Verification Engineer (Technical role) Position Description: As a technical member of Micron's ASIC Design Verification team, you will have a key role in development of advanced ...
Senior ASIC Design Verification Engineer (Technical role) Position Description: As a technical member of Micron's ASIC Design Verification team, you will have a key role in development of advanced ...
Senior ASIC Design Verification Engineer (Technical role) Position Description: As a technical member of Micron's ASIC Design Verification team, you will have a key role in development of advanced ...
Senior ASIC Design Verification Engineer (Technical role) Position Description: As a technical member of Micron's ASIC Design Verification team, you will have a key role in development of advanced ...
Duties and Tasks: • Responsible for definition, design, verification and documentation for FPGA ... ASIC/FPGA engineering processes • Keeps abreast of technology trends in ASIC/FPGA • ...
New
Duties and Tasks: • Responsible for definition, design, verification and documentation for FPGA ... ASIC/FPGA engineering processes • Keeps abreast of technology trends in ASIC/FPGA • ...
New
Senior ASIC Design Verification Engineer (Technical role) Position Description: As a technical member of Micron's ASIC Design Verification team, you will have a key role in development of advanced ...
Senior ASIC Design Verification Engineer (Technical role) Position Description: As a technical member of Micron's ASIC Design Verification team, you will have a key role in development of advanced ...
Senior ASIC Design Verification Engineer (Technical role) Position Description: As a technical member of Micron's ASIC Design Verification team, you will have a key role in development of advanced ...
Senior ASIC Design Verification Engineer (Technical role) Position Description: As a technical member of Micron's ASIC Design Verification team, you will have a key role in development of advanced ...
| Aspect | Contractual Asic Rtl Design Engineer | Digital IC Design Engineer |
|---|---|---|
| Credentials | Bachelor's/Master's in Electrical Engineering or Computer Engineering | Bachelor's/Master's in Electrical Engineering or Computer Engineering |
| Work Environment | Contract-based, project-specific, often in semiconductor or tech companies | Full-time or contract, working on digital integrated circuit design |
| Industry Usage | Common in semiconductor, electronics, and tech firms for ASIC development | Used across semiconductor, consumer electronics, and communication industries |
Both roles require similar educational backgrounds and work in related environments, focusing on digital circuit design. The main difference is that Contractual Asic Rtl Design Engineers typically work on specific ASIC projects on a contractual basis, while Digital IC Design Engineers may have broader responsibilities in digital chip development, often in full-time roles.
$140K - $170K/yr
Other
Medical, Retirement, PTO
Posted 26 days ago